公开(公告)号：US07075261B2

公开(公告)日：2006-07-11

申请号：US10119983

申请日：2002-04-10

Applicant: Steven Burstein

Inventor： Steven Burstein

IPC: G05B5/00 ,  G05D23/00

CPC classification number: H02P1/04 ,  F04D27/008 ,  Y10S388/911

Abstract: A method and apparatus for controlling a fan is disclosed. In one embodiment, a method for controlling a fan includes applying power to the fan at startup. The fan may be supplied a predetermined amount of current, which may break the inertia of the fan propeller and begin its rotation. As the propeller begins rotating, the speed at which it rotates may be monitored. The fan startup routine may continue until the fan reaches or exceeds a minimum fan speed threshold. Once the fan has at least reached the minimum speed, the amount of current supplied to the fan may be reduced such that the fan rotates at minimum speed, and an automatic fan control algorithm may begin executing. By reducing the current such that the fan operates at a minimum speed, the amount of audible noise generated by the fan during startup may be kept to a minimum level.

公开(公告)号：US07009443B2

公开(公告)日：2006-03-07

申请号：US10862675

申请日：2004-06-07

Applicant: Paul F. Illegems

Inventor： Paul F. Illegems

IPC: H01H85/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: In one embodiment, a system comprises a programming unit coupled to at least one programmable fuse and configured to program the programmable fuse. In addition, the system comprises a monitoring circuit coupled to the programmable fuse and configured to monitor electrical characteristics associated with the programmable fuse while the programmable fuse is being programmed. In one embodiment, the monitoring circuit is configured to detect a voltage associated with the programmable fuse. Furthermore, the monitoring circuit is configured to compare the detected voltage associated with the programmable fuse with a predetermined voltage value (i.e., endpoint detection). If the detected voltage is equal to or less than the predetermined voltage value, the monitoring circuit is configured to change a state of a control signal to stop the programming of the programmable fuse. Otherwise, the programming unit continues to program the programmable fuse.

Abstract translation: 在一个实施例中，系统包括耦合到至少一个可编程熔丝并被配置为对可编程熔丝进行编程的编程单元。 此外，该系统包括耦合到可编程熔丝的监控电路，并且被配置为在编程可编程熔丝的同时监视与可编程熔丝相关联的电特性。 在一个实施例中，监视电路被配置为检测与可编程保险丝相关联的电压。 此外，监视电路被配置为将与可编程熔丝相关联的检测电压与预定电压值（即端点检测）进行比较。 如果检测到的电压等于或小于预定电压值，则监视电路被配置为改变控制信号的状态以停止可编程熔丝的编程。 否则，编程单元继续编程可编程保险丝。

公开(公告)号：US20060039408A1

公开(公告)日：2006-02-23

申请号：US10924211

申请日：2004-08-23

Applicant: Klaas Wortel ,  Richard Wahler ,  Andrew Lueck

Inventor： Klaas Wortel ,  Richard Wahler ,  Andrew Lueck

IPC: H04J3/16

CPC classification number: G06F13/4282 ,  G06F1/206 ,  H04L7/04

Abstract: A single-wire bus protocol named Budget Sensor Bus (BBUS) for simplified system management. The BBUS may transmit information packets in NRZ format from a monitored device/circuit to a host. In one embodiment, each packet comprises a start sequence, a data type, a device or register number, device data, and a stop sequence. The BBUS may directly transmit raw data bits from the monitored device/circuit to the host and may use the start sequence to communicate to the host the bit frequency that is used by the monitored device/circuit. Following the start sequence the host may get in sync with the monitored device/circuit and may be enabled to directly read the data bits that follow. The BBUS may provide a means for the monitored device/circuit to immediately transfer device information to the host. All functions and operations required to interpret the device information may reside within the host. The BBUS may transmit information packets from the monitored device/circuit to the host, but not from the host to the monitored device/circuit. In one embodiment the BBUS is used for thermal management, where the monitored device/circuit comprises temperature/voltage sensors, the host is an SIO controller, and temperature/voltage data is transmitted from the sensors to the SIO controller.

Abstract translation: 一种名为Budget Sensor Bus（BBUS）的单线总线协议，用于简化系统管理。 BBUS可以将NRZ格式的信息包从被监视的设备/电路传输到主机。 在一个实施例中，每个分组包括起始序列，数据类型，设备或寄存器号，设备数据和停止序列。 BBUS可以将原始数据位从监视的设备/电路直接发送到主机，并且可以使用起始序列向主机通信被监视的设备/电路使用的位频。 在启动顺序之后，主机可以与被监视的设备/电路同步，并且可以使能直接读取随后的数据位。 BBUS可以为监控的设备/电路提供一种手段，将设备信息立即传送到主机。 解释设备信息所需的所有功能和操作都可能驻留在主机内。 BBUS可以将来自被监视设备/电路的信息分组传送到主机，而不是从主机传输到被监控设备/电路。 在一个实施例中，BBUS用于热管理，其中所监视的设备/电路包括温度/电压传感器，主机是SIO控制器，并且温度/电压数据从传感器传输到SIO控制器。

公开(公告)号：US06937100B2

公开(公告)日：2005-08-30

申请号：US10739797

申请日：2003-12-18

Applicant: Thomas R. Anderson

Inventor： Thomas R. Anderson

IPC: H03F3/45

CPC classification number: H03F3/45183

Abstract: An amplifier circuit. In one embodiment, the amplifier circuit includes an output stage and a gain stage. The gain stage includes first and second differential output terminals that may be coupled to first and second differential input terminals of the output stage. The gain stage includes a first feedback loop and a second feedback loop. First and second half-stages within the gain stage may be coupled to provide the second feedback loop. The first half-stage may be coupled to control a first output current at the first output terminal of the gain stage, while the second-half-stage may be coupled to control a second output current at the second output terminal of the gain stage.

公开(公告)号：US06924760B1

公开(公告)日：2005-08-02

申请号：US10789903

申请日：2004-02-27

Applicant: Scott C. McLeod ,  Aniruddha Bashar

Inventor： Scott C. McLeod ,  Aniruddha Bashar

IPC: H03M1/06 ,  H03M1/66 ,  H03M1/80 ,  H03M3/04

CPC classification number: H03M1/066 ,  H03M1/466 ,  H03M1/804 ,  H03M3/464 ,  H03M3/502

Abstract: In one set of embodiments the invention comprises a highly accurate, low-power, compact size DAC utilizing charge redistribution techniques. Two complementary conversions may be performed and added together to form a final DAC output voltage by performing charge redistribution a first time, and again a second time in a complementary fashion, followed by a summing of the two charge distributions, in effect canceling the odd order capacitor mismatch errors. By canceling all odd order mismatch errors the accuracy of the DAC may become a function of the square of the mismatch of the two capacitors, resulting in greatly increased accuracy. When performing the complementary conversions for multiple bits, the sequence in which each of the two capacitors is charged may be determined to minimize the even-order errors, especially second-order errors. The DEM technique may be applied, in conjunction with the complementary conversions, with less oversampling than required by current DEM implementations, resulting in even-order errors being substantially reduced in addition to all odd-order errors being eliminated.

Abstract translation: 在一组实施例中，本发明包括使用电荷再分配技术的高精度，低功率，紧凑尺寸的DAC。 可以通过第一次执行电荷重新分配并且以互补方式再次进行第二次，然后将两个电荷分布相加，实际上消除了奇数阶，可以执行两个互补转换并相加在一起形成最终的DAC输出电压 电容器失配误差。 通过消除所有奇数阶失配误差，DAC的精度可能成为两个电容器失配的平方的函数，从而大大增加了精度。 当对多个位执行互补转换时，可以确定两个电容器中的每一个被充电的顺序，以将偶数误差，特别是二阶误差最小化。 DEM技术可以与互补转换一起应用于比当前DEM实现所要求的更少的过采样，导致除了消除所有奇数误差之外，偶数阶误差被显着降低。

公开(公告)号：US06883105B2

公开(公告)日：2005-04-19

申请号：US10004390

申请日：2001-10-25

Applicant: Drew J. Dutton

Inventor： Drew J. Dutton

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3215

Abstract: A method and apparatus for configuration control and power management through special signaling is provided. In one embodiment, a computer system may include a processor and a plurality of devices that may act as a source device, a destination device, or both. A particular source device may be configured for communications with a destination device. The source device may further be configured to violate one or more known communications rules when communicating the with the destination device. The destination device may be configured to detect the violation. The violation of a known communications rule by the source device may indicate a pending change of state in the computer system, or that a change of state has occurred.

Abstract translation: 提供了一种通过特殊信令进行配置控制和电源管理的方法和装置。 在一个实施例中，计算机系统可以包括可以充当源设备，目的地设备或两者的处理器和多个设备。 可以将特定源设备配置为与目的地设备进行通信。 源设备还可以被配置为在与目的地设备通信时违反一个或多个已知通信规则。 目的地设备可以被配置为检测违规。 由源设备违反已知的通信规则可以指示计算机系统中的待决状态改变，或者已经发生状态改变。

公开(公告)号：US5790873A

公开(公告)日：1998-08-04

申请号：US685376

申请日：1996-07-23

Applicant: Jay D. Popper ,  Richard E. Wahler

Inventor： Jay D. Popper ,  Richard E. Wahler

IPC: G06F1/26 ,  G06F12/16 ,  H02J9/00 ,  H02J9/06 ,  G06F1/30

CPC classification number: H02J9/005 ,  G06F1/26 ,  H02J9/06 ,  Y10T307/625

Abstract: A method and apparatus for providing power management functions in a computer or other electronic system which includes a primary power supply, a trickle power supply and a battery back-up power supply. A power management circuit includes a storage element which stores an indication of the current turn-on or turn-off condition of the primary power supply. The power management circuit also includes a group of logic gates which process signals which are supplied to the storage element under normal operating conditions to control the turn-on or turn-off condition of the primary power supply. The power management circuit senses when the trickle supply is deactivated due to a line power failure or the like, and subsequently switches the power supply inputs of the storage element and certain of the logic gates from the trickle supply to the battery back-up supply. A blocking signal is generated which prevents those signals which require the trickle supply for logic integrity from being applied to the storage element. In this manner, only signals which do not require the trickle supply for logic integrity are applied to the storage element while the trickle supply is deactivated.

Abstract translation: 一种用于在包括主电源，涓流电源和电池备用电源的计算机或其他电子系统中提供电源管理功能的方法和装置。 电源管理电路包括存储元件，其存储主电源的当前导通或关断状态的指示。 功率管理电路还包括一组逻辑门，其处理在正常工作条件下提供给存储元件的信号，以控制主电源的导通或关断状态。 电源管理电路由于线路电源故障等而感知到涓流电源何时停止，并且随后将存储元件的电源输入和某些逻辑门从涓流供应切换到电池备用电源。 产生阻塞信号，其阻止需要向逻辑完整性提供涓流供应的那些信号被施加到存储元件。 以这种方式，只有不需要用于逻辑完整性的涓流供应的信号被施加到存储元件，同时涓流供应被去激活。

公开(公告)号：US5682383A

公开(公告)日：1997-10-28

申请号：US762299

申请日：1996-12-09

Applicant: Ashraf Mansur Dahod ,  Erick R. Diaz ,  Camillo Iadevaia ,  Ronald Sulyma ,  Colin Michael Taddonio

Inventor： Ashraf Mansur Dahod ,  Erick R. Diaz ,  Camillo Iadevaia ,  Ronald Sulyma ,  Colin Michael Taddonio

IPC: H04L12/44 ,  H04L12/46 ,  H04J12/28

CPC classification number: H04L12/44 ,  H04L12/46

Abstract: An arrangement for interconnecting groups of users into collision domains in a Local Area Network such as an Ethernet comprises a plurality of repeater groups, with each repeater group being connected to a group of user stations. The arrangement also comprises an electronically reconfigurable switch matrix. The switch matrix comprises a plurality of segment lines (or other transmission media) each of which is used to form one collision domain or Ethernet segment. Switch elements under the control of a microcontroller selectively connect particular repeater groups (and the associated user groups) to particular segment lines to form Ethernet segments, each Ethernet segment being a single collision domain. Internetworking devices such as bridges and routers may also be connected to the switch matrix to interconnect particular collision domains.

Abstract translation: 用于将诸如以太网的局域网中的用户组互连到冲突域的布置包括多个中继器组，每个中继器组连接到一组用户站。 该装置还包括电子可重构开关矩阵。 交换矩阵包括多个分段线路（或其它传输媒体），每个分段线路用于形成一个冲突域或以太网分段。 在微控制器下的开关元件选择性地将特定的中继器组（和相关用户组）连接到特定的分段线以形成以太网段，每个以太网段是单个冲突域。 诸如网桥和路由器之类的互联设备也可以连接到交换机矩阵以互连特定的冲突域。

公开(公告)号：US5664108A

公开(公告)日：1997-09-02

申请号：US638304

申请日：1996-04-26

Applicant: Robert Heaton ,  Nariman Yousefi ,  Khosrow Sadeghi ,  David Fischer

Inventor： Robert Heaton ,  Nariman Yousefi ,  Khosrow Sadeghi ,  David Fischer

IPC: H04L7/06 ,  H04L12/413 ,  H04L12/44 ,  G06F13/00

CPC classification number: H04L12/44 ,  H04L12/413 ,  H04L7/06 ,  Y10S370/902

Abstract: In a fast Ethernet, each station is connected to the hub by four unshielded twisted pairs. A first pair is transmit only for the station and receive only for the hub, a second pair is transmit only for the hub and receive only for the station, and the third and fourth pairs are bidirectional. Both the station and the hub use their transmit only and the bidirectional pairs for data transmission and their receive only pair for collision detection.

Abstract translation: 在快速以太网中，每个站通过四个非屏蔽双绞线连接到集线器。 第一对是仅为站发送并且仅为集线器接收，第二对仅针对集线器进行发送，并仅为站接收，并且第三和第四对是双向的。 站和集线器都使用它们的发送和双向对进行数据传输，并且它们的接收只对用于冲突检测。

公开(公告)号：US5448598A

公开(公告)日：1995-09-05

申请号：US88008

申请日：1993-07-06

Applicant: Nariman Yousefi ,  Benjamin E. Nise ,  Kelly P. McClellan

Inventor： Nariman Yousefi ,  Benjamin E. Nise ,  Kelly P. McClellan

IPC: H03L7/089 ,  H04L7/033 ,  H04L7/00 ,  H03D3/24 ,  H04L25/36 ,  H04L25/40

CPC classification number: H04L7/033 ,  H03L7/0898

Abstract: A VSLI transceiver chip incorporating an improved analog PLL circuit for recovering a digital clock signal from a digital data signal having pulse widths which may vary during each data cycle. The analog PLL clock recovery circuit comprises a phase detector, a gain control circuit, a variable current charge pump, a loop filter and a variable frequency oscillator. The phase detection means for detecting, during each data cycle, the phase error between the digital data signal and recovered digital clock signal, and produces first end second digital control pulse signals in response to the detection of the phase error. The gain control means produces third and fourth digital control pulse signals during each data cycle. The value of the third and fourth control pulse signals during each data cycle depends on the value of the digital data signal, the value of the recovered clock signal, and the value of the second digital control pulse signal during the data cycle, and the change in value of the third and fourth control pulse signals is responsive to the change in the value of the recovered digital clock signal. The variable current charge pump receives the first and second digital control pulse signals. The recovered digital clock signal is produced by variable frequency oscillator, having a clock frequency proportional to the produced analog control signal.

Abstract translation: VSLI收发器芯片包含改进的模拟PLL电路，用于从具有在每个数据周期期间可能变化的脉冲宽度的数字数据信号中恢复数字时钟信号。 模拟PLL时钟恢复电路包括相位检测器，增益控制电路，可变电流电荷泵，环路滤波器和可变频率振荡器。 相位检测装置，用于在每个数据周期期间检测数字数据信号与恢复的数字时钟信号之间的相位误差，并响应于相位误差的检测产生第一端第二数字控制脉冲信号。 增益控制装置在每个数据周期期间产生第三和第四数字控制脉冲信号。 在每个数据周期期间，第三和第四控制脉冲信号的值取决于数据数据信号的值，恢复的时钟信号的值和数据周期期间的第二数字控制脉冲信号的值， 第三和第四控制脉冲信号的输入值响应于恢复的数字时钟信号的值的变化。 可变电流电荷泵接收第一和第二数字控制脉冲信号。 恢复的数字时钟信号由可变频率振荡器产生，具有与所产生的模拟控制信号成比例的时钟频率。