公开(公告)号：US09276610B2

公开(公告)日：2016-03-01

申请号：US14165505

申请日：2014-01-27

Applicant: Tensorcom, Inc.

Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

IPC: H03M13/11

CPC classification number: H03M13/1145 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/1148 ,  H03M13/116

Abstract: The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.

Abstract translation: 该架构能够切换到具有比阻塞CNU调度架构更好的性能的非阻塞校验节点更新（CNU）调度体系结构。 该架构使用Beta = 1的偏移最小和，时钟域工作在440 MHz。 约束宏矩阵是备用矩阵，其中每个“1”对应于作为单位矩阵的移位版本的循环移位单位矩阵的子阵列。 在分层架构中使用四个核心处理器，约束矩阵在168×672位的宏阵列中使用42（校验节点）×42（变量节点）的子阵列。 使用管道处理，其中每层的延迟只需要4个时钟周期。

公开(公告)号：US09264056B2

公开(公告)日：2016-02-16

申请号：US14672214

申请日：2015-03-29

Applicant: Tensorcom, Inc.

Inventor： Dai Dai

IPC: H03M1/12 ,  H03M1/00 ,  H03K5/24 ,  H03M1/08 ,  H03M1/18 ,  H03H11/48

CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

Abstract translation: 可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器的输入差分栅极电容和差分金属层迹线加载，以将这些比较器与PGA互连。 提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。 为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。 该取消扩展了PGA输出与比较器的第一级的输入之间的互连的增益特性。 有源负电容由交叉对NMOS组成，其中电容器连接其源极，其中每个NMOS由电流源偏置。

公开(公告)号：US20150214980A1

公开(公告)日：2015-07-30

申请号：US14165505

申请日：2014-01-27

Applicant: Tensorcom, Inc.

Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

IPC: H03M13/11

CPC classification number: H03M13/1145 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/1148 ,  H03M13/116

Abstract: The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.

Abstract translation: 该架构能够切换到具有比阻塞CNU调度架构更好的性能的非阻塞校验节点更新（CNU）调度体系结构。 该架构使用Beta = 1的偏移最小和，时钟域工作在440 MHz。 约束宏矩阵是备用矩阵，其中每个“1”对应于作为单位矩阵的移位版本的循环移位单位矩阵的子阵列。 在分层架构中使用四个核心处理器，约束矩阵在168×672位的宏阵列中使用42（校验节点）×42（变量节点）的子阵列。 使用管道处理，其中每层的延迟只需要4个时钟周期。

公开(公告)号：US08836407B1

公开(公告)日：2014-09-16

申请号：US13789681

申请日：2013-03-08

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe ,  Tham KhongMeng

IPC: G06F7/44 ,  G06G7/16

CPC classification number: G06G7/16 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0019

Abstract: A cross coupled NMOS transistors providing a negative gm transistor feedback allows a mixer to saturate at a reduced input signal swing voltage when compared to a conventional mixer allowing the mixer to enter into the current mode operation at a reduced signal input voltage range. The linearity of the baseband signal path can be traded against the mixer gain and is improved if the signal swing in the baseband signal path is reduced. The input mixer transistors operate in the saturated mode at a reduced input signal swing voltage causing the power efficiency of the system to increase since the transmit chain operates at a class-D power efficient. Efficiency is very important in mobile applications to save and extend the battery power of a mobile phone providing a better utilization of the available power since most of that power is supplied to the energy of the outgoing modulated signal.

Abstract translation: 提供负gm晶体管反馈的交叉耦合NMOS晶体管使混频器能够与传统的混频器相比，作为降低的输入信号摆幅电压饱和，从而允许混频器在降低的信号输入电压范围内进入电流模式操作。 基带信号路径的线性度可以抵抗混频器增益进行交易，如果基带信号路径中的信号摆幅减小，则可以得到改善。 输入混频器晶体管以降低的输入信号摆幅电压在饱和模式下工作，导致系统的功率效率增加，因为发射链以D类功率有效工作。 在移动应用中，效率对于节省和扩展移动电话的电池电力是非常重要的，其提供了对可用功率的更好的利用，因为大部分功率被提供给输出调制信号的能量。

公开(公告)号：US20140062621A1

公开(公告)日：2014-03-06

申请号：US13602216

申请日：2012-09-03

Applicant: Dai Dai

Inventor： Dai Dai

IPC: H03H11/44

CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital converters (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancellation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

Abstract translation: 可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器的输入差分栅极电容和差分金属层迹线加载，以将这些比较器与PGA互连。 提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。 为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。 这种消除延长了PGA输出与比较器的第一级的输入之间的互连的增益特性。 有源负电容由交叉对NMOS组成，其中电容器连接其源极，其中每个NMOS由电流源偏置。

公开(公告)号：US20130307613A1

公开(公告)日：2013-11-21

申请号：US13474742

申请日：2012-05-18

Applicant: KhongMeng Tham

Inventor： KhongMeng Tham

IPC: H03B1/04

CPC classification number: H03B1/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B2202/04 ,  H03B2202/088

Abstract: This invention compensates for the unintentional magnetic coupling between a first and second inductor of two different closely spaced inductors separated by a conversion circuit. A cancellation circuit formed from transistors senses the magnetic coupling in the first inductor and feeds a current opposite to the induced magnetic coupling captured by the second inductor such that the coupled magnetic coupling can be compensated and allows the first and second inductors to behave independently with regards to the coupled magnetic coupling between the first and second inductors. This allows the distance between the first and second inductors to be minimized which saves silicon area. In addition, the performance is improved since the overall capacitance in both circuits can be decreased. This cancellation technique to reduce the magnetic coupling between two closed placed inductively loaded circuits allows the design of a more compact and faster performing circuit.

Abstract translation: 本发明补偿由转换电路分离的两个不同紧密间隔的电感器的第一和第二电感器之间的无意的磁耦合。 由晶体管形成的消除电路感测第一电感器中的磁耦合，并且馈送与由第二电感器捕获的感应磁耦合相反的电流，使得耦合的磁耦合可以被补偿，并允许第一和第二电感器独立地表现， 耦合到第一和第二电感器之间的耦合磁耦合。 这允许第一和第二电感器之间的距离最小化，从而节省了硅面积。 此外，由于可以降低两个电路中的整体电容，性能得到改善。 这种减少两个闭合放置的感应加载电路之间的磁耦合的消除技术允许设计更紧凑和更快的执行电路。

公开(公告)号：US20130266045A1

公开(公告)日：2013-10-10

申请号：US13442387

申请日：2012-04-09

Applicant: Ismail Lakkis

Inventor： Ismail Lakkis

IPC: H04B1/38

CPC classification number: H04B1/525 ,  H04B1/123 ,  H04B1/30

Abstract: Transceiver calibration is a critical issue for proper transceiver operation. The transceiver comprises at least one RF transmit chain and one RF receive chain. A closed loop path is formed from the digital block, the RF transmit chain, the substrate coupling, the RF receive chain back to the digital block and is used to estimate and calibrate the transceiver parameters over the operating range of frequencies. The substrate coupling eliminates the need for the additional circuitry saving area, power, and performance. In place of the additional circuitry, the digital block which performs baseband operations can be reconfigured into a software or/and hardware mode to calibrate the transceiver. The digital block comprises a processor and memory and is coupled to the front end of the RF transmit chain and the tail end of the RF receive chain.

Abstract translation: 收发器校准是正确的收发器操作的关键问题。 收发器包括至少一个RF发射链和一个RF接收链。 从数字模块，RF发射链，衬底耦合，RF接收链回到数字模块形成闭环路径，并用于在频率的工作范围内估计和校准收发器参数。 基板耦合消除了额外的电路节省面积，功率和性能的需要。 代替附加电路，执行基带操作的数字模块可以重新配置成软件或/和硬件模式，以校准收发器。 数字模块包括处理器和存储器，并且耦合到RF发射链的前端和RF接收链的尾端。

公开(公告)号：US20130076434A1

公开(公告)日：2013-03-28

申请号：US13243880

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H03B1/00 ,  H03F3/45

CPC classification number: H03H11/1217 ,  H03F3/195 ,  H03F3/301 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03H3/00

Abstract: A Sallen-Key filter requires an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. The operational amplifier requires an internal feedback path for stability that limits performance. This invention eliminates the need for internal feedback and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.

Abstract translation: Sallen-Key滤波器需要具有大输入阻抗和小输出阻抗的运算放大器，以满足外部滤波器特性。 运算放大器需要一个内部反馈路径来稳定性，从而限制性能。 本发明消除了对内部反馈的需要，并且增加了具有与Sallen-Key滤波器中的运算放大器匹配的特性的源极跟随器的增益。 源极跟随器提供6 dB的交流电压增益，并代替Sallen-Key滤波器中的运算放大器。 Sallen-Key滤波器需要差分配置，以产生所有需要的信号，并在前馈路径中使用这些信号。 此外，由于源极跟随器仅使用两个n沟道堆叠器件，因此在40nm CMOS技术中，1.2V电压源的裕量电压最大可达数百毫伏。 因此，Sallen-Key滤波器所需的880 MHz带宽可以使用创新的源跟踪器轻松实现。

公开(公告)号：US20110295102A1

公开(公告)日：2011-12-01

申请号：US13151248

申请日：2011-06-01

Applicant: Ismail Lakkis ,  Hock Law

Inventor： Ismail Lakkis ,  Hock Law

IPC: A61B5/00 ,  A61B5/01

CPC classification number: H04W56/0015 ,  A61B5/00 ,  A61B5/0002 ,  A61B5/002 ,  A61B5/0022 ,  A61B5/0024 ,  A61B5/0026 ,  A61B5/0028 ,  A61B5/0059 ,  A61B5/01 ,  A61B5/02028 ,  A61B5/0205 ,  A61B5/02055 ,  A61B5/021 ,  A61B5/02438 ,  A61B5/0507 ,  A61B5/0816 ,  A61B5/11 ,  A61B5/4362 ,  A61B5/6833

Abstract: A medical sensor system comprises a gateway comprising a wideband receiver and a narrow band transmitter, the each gateway configured to receive a wideband positioning frame using the wideband receiver from one or more wearable sensors and to transmit acknowledgement frames using the narrow band transmitter that include timing and control data for use by the sensors to establish timing for transmission of the positioning frame; and at least one wearable sensor comprising a wideband transmitter and a narrow band receiver, the sensor configured to transmit a sensor data frame to the gateway using the wideband transmitter and to receive an acknowledgement frame from the gateway using the narrow band receiver, extract timing and control information from the frame, and adjust the timing and synchronization of the wideband transmitter using the timing and control information.

Abstract translation: 医疗传感器系统包括包括宽带接收机和窄带发射机的网关，每个网关被配置为使用来自一个或多个可佩戴传感器的宽带接收机接收宽带定位帧，并且使用包括定时的窄带发射机发送确认帧 以及由传感器使用的控制数据，以建立定位框架的传输定时; 以及包括宽带发射机和窄带接收机的至少一个可佩戴传感器，所述传感器被配置为使用所述宽带发射机向所述网关发送传感器数据帧，并且使用所述窄带接收机从所述网关接收确认帧，提取定时和 控制来自帧的信息，并使用定时和控制信息来调整宽带发射机的定时和同步。

公开(公告)号：US12027775B2

公开(公告)日：2024-07-02

申请号：US18230496

申请日：2023-08-04

Applicant: Tensorcom, Inc.

Inventor： Guang-Fu Cheng

IPC: H01Q21/06 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q21/00 ,  H01Q1/24

CPC classification number: H01Q21/067 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q21/0006 ,  H01Q21/0087 ,  H01Q1/241

Abstract: An antenna array system and a method for making the antenna system. The system includes at least two antenna elements serving as transmitter elements, and at least two antenna elements serving as receiver elements. Each of the transmitter antenna and receiver antenna elements include a pair of curved arms, wherein a first arm in the pair of curved arms is configured to be connected from a signal trace of the antenna system. The second arm in the pair of curved arms is configured to be connected to a ground plane.