公开(公告)号：US20080315439A1

公开(公告)日：2008-12-25

申请号：US12201236

申请日：2008-08-29

Applicant: Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

Inventor： Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

IPC: H01L23/52

CPC classification number: H01L21/6835 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49534 ,  H01L23/49558 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.

Abstract translation: 提供了包括图案化导电层，第一阻焊层，芯片，多个接合线和模塑料的四平坦非导体（QFN）芯片封装。 图案化导电层具有彼此相对的第一表面和第二表面。 第一阻焊层设置在第一表面上，其中第一表面的一部分被第一阻焊层暴露。 芯片设置在第一阻焊层上，其中第一阻焊层位于图案化导电层和芯片之间。 接合线与第一阻焊层暴露的芯片和图案化的导电层电连接。 模塑料封装图形导电层，第一阻焊层，芯片和接合线。

公开(公告)号：US20080265400A1

公开(公告)日：2008-10-30

申请号：US11872169

申请日：2007-10-15

Applicant: Yu-Tang Pan ,  Shih-Wen Chou ,  Chun-Ying Lin

Inventor： Yu-Tang Pan ,  Shih-Wen Chou ,  Chun-Ying Lin

IPC: H01L23/04 ,  H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00

Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer.

Abstract translation: 提供了一种芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，电路板和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源表面和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到基板的第一表面。 电路板具有设置在第一后表面上的电介质层，并且设置在电介质层上的图案化导电层经由接合线电连接至基板。 设置在图案化导电层上的第二芯片具有形成在其第二有源表面上的多个第二焊盘，并且折叠地连接到图案化的导电层。

公开(公告)号：US20080157333A1

公开(公告)日：2008-07-03

申请号：US11746654

申请日：2007-05-10

Applicant: Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

Inventor： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

IPC: H01L21/00 ,  H01L23/24

CPC classification number: H01L21/563 ,  H01L23/3135 ,  H01L24/97 ,  H01L33/642 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip package including a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer is provided. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

Abstract translation: 包括热增强板的芯片封装，在热增强板周围接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和 提供设置在膜状电路层上的至少一个芯片。 导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。 芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。 第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。 因此，提高了发光芯片封装的散热效率。

公开(公告)号：US20070267756A1

公开(公告)日：2007-11-22

申请号：US11543052

申请日：2006-10-05

Applicant: I-Hsin Mao ,  Ya-Chi Chen ,  Chun-Ying Lin ,  Yu-Ren Chen

Inventor： I-Hsin Mao ,  Ya-Chi Chen ,  Chun-Ying Lin ,  Yu-Ren Chen

IPC: H01L23/52

CPC classification number: H01L23/49531 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An IC package with a defined wire-bonding region primarily comprises a multi-layer lead frame with a plurality of leads, a chip, a plurality of bonding wires within the wire-bonding region, and at least an electrical transition component outside the wire-bonding region. At least a transition finger is carried on one of the lead and is electrically isolated from the corresponding carrying lead without covering inner end of the carrying lead. The parts of the electrical transition component electrically connects the transition finger to another lead that is not directly below the transition finger to reduce the crossings of the bonding wires or to increase the vertical distances between the bonding wires at the crossings to avoid electrical shorts between the bonding wires during encapsulation.

Abstract translation: 具有限定的引线键合区域的IC封装主要包括具有多个引线的多层引线框架，芯片，引线接合区域内的多个接合线，以及至少一个引线接合区域外的电过渡部件， 接合区域。 至少一个过渡指状物承载在一个引线上，并且与相应的承载导线电隔离，而不覆盖承载引线的内端。 电过渡部件的部分将过渡指状物电连接到不是过渡指状物下方的另一导线，以减少接合线的交叉，或者增加在交叉处的接合线之间的垂直距离，以避免在两者之间的电短路 封装期间接合线。