公开(公告)号：US08324668B2

公开(公告)日：2012-12-04

申请号：US12640700

申请日：2009-12-17

Applicant: Li-Ping Huang ,  Chih-Hsiang Huang ,  Ka Hing Fung ,  Chung-Cheng Wu ,  Haiting Wang

Inventor： Li-Ping Huang ,  Chih-Hsiang Huang ,  Ka Hing Fung ,  Chung-Cheng Wu ,  Haiting Wang

IPC: H01L29/76

CPC classification number: H01L27/0207 ,  H01L21/28123 ,  H01L21/823878 ,  H01L27/092

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition.

Abstract translation: 本发明提供集成电路。 集成电路包括具有第一组成的第一晶体管的第一操作装置; 第二操作装置，具有第一组合物的第二晶体管; 以及设置在所述第一和第二晶体管之间的隔离晶体管，所述隔离晶体管具有不同于所述第一组成的第二组成。

公开(公告)号：US20110291197A1

公开(公告)日：2011-12-01

申请号：US12787966

申请日：2010-05-26

Applicant: Chung-Cheng WU ,  Ali KESHAVARZI ,  Ka Hing FUNG ,  Ta-Pen GUO ,  Jiann-Tyng TZENG ,  Yen-Ming CHEN ,  Shyue-Shyh LIN ,  Shyh-Wei WANG ,  Sheng-Jier YANG ,  Hsiang-Jen TSENG ,  David B. SCOTT ,  Min CAO

Inventor： Chung-Cheng WU ,  Ali KESHAVARZI ,  Ka Hing FUNG ,  Ta-Pen GUO ,  Jiann-Tyng TZENG ,  Yen-Ming CHEN ,  Shyue-Shyh LIN ,  Shyh-Wei WANG ,  Sheng-Jier YANG ,  Hsiang-Jen TSENG ,  David B. SCOTT ,  Min CAO

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/7848 ,  H01L2224/16225

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.

Abstract translation: 集成电路包括用于第一类型晶体管的第一扩散区域。 第一类型晶体管包括第一漏极区域和第一源极区域。 用于第二类型晶体管的第二扩散区域与第一扩散区域间隔开。 第二类型晶体管包括第二漏极区域和第二源极区域。 栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。 第一金属层与第一源区电耦合。 第一金属层和第一扩散区域与第一距离重叠。 第二金属层与第一漏极区域和第二漏极区域电耦合。 第二金属层和第一扩散区域与第二距离重叠。 第一距离大于第二距离。

公开(公告)号：US20080028700A1

公开(公告)日：2008-02-07

申请号：US11496621

申请日：2006-08-01

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: E04B7/18

CPC classification number: E04D3/08 ,  A01G9/16 ,  E04D2003/0806 ,  E04D2003/085 ,  Y02A40/254

Abstract: The invention relates to an assembled greenhouse structure, mainly comprised of a frame structure and a transparent or translucent sheet material that is disposed on the frame; the characteristic of the invention lies in that the frame for positioning said sheet material is composed of a stand, roof sheathing, and connectors; the stand and the roof sheathing are formed as aluminum alloy extrusions, the connectors are an elastic member, having one end thereof embedded in a sliding slot on the inner side of the roof sheathing, and the other end thereof has an elastic hook portion vertically inserted in a slot coupling corresponding to the stand. Accordingly, the invention disclosed herein achieves the objectives of presenting a pleasant appearance from the exterior and with the advantage of rapid assembly of the greenhouse.

Abstract translation: 本发明涉及一种组装的温室结构，主要由框架结构和布置在框架上的透明或半透明板材构成; 本发明的特征在于用于定位所述片材的框架由支架，屋顶护套和连接器组成; 支架和屋顶护套形成为铝合金挤压件，连接器是弹性件，其一端嵌入屋顶护套内侧的滑动槽中，另一端具有垂直插入的弹性钩部 在与支架相对应的狭槽联接中。 因此，本文公开的发明实现了从外部呈现愉悦的外观并且具有快速组装温室的优点的目的。

公开(公告)号：US20070024251A1

公开(公告)日：2007-02-01

申请号：US11242915

申请日：2005-10-05

Applicant: Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

Inventor： Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

IPC: G05F1/00

CPC classification number: G05F1/70

Abstract: The continuous conduction mode (CCM) boost voltage power factor correction apparatus with an average-current control mode of the present invention uses resettable integrators to integrate the difference voltage signal outputted from the voltage error amplifier and the input current signal obtained from detection. The integration results are then compared to control the duty cycle of the switch. Thereby, the input current and the input voltage in the AC/DC electrical power converter have a proportion relation and their phases are the same as each other. The components used in this control method are simpler than the PFC circuit of the prior art. It is easy to integrate in one chip with fewer pins. The apparatus of the present invention has a high power factor and a low total harmonic distortion (THD).

Abstract translation: 具有本发明的平均电流控制模式的连续导通模式（CCM）升压电压功率因数校正装置使用可复位积分器来积分从电压误差放大器输出的差分电压信号和从检测获得的输入电流信号。 然后将积分结果进行比较，以控制开关的占空比。 因此，AC / DC电力转换器的输入电流和输入电压具有比例关系，它们的相位彼此相同。 在该控制方法中使用的部件比现有技术的PFC电路简单。 在一个芯片中集成更少的引脚很容易。 本发明的装置具有高功率因数和低总谐波失真（THD）。

公开(公告)号：US20060115938A1

公开(公告)日：2006-06-01

申请号：US11001514

申请日：2004-11-30

Applicant: Chung-Cheng Wu ,  Wen-Ting Chu

Inventor： Chung-Cheng Wu ,  Wen-Ting Chu

IPC: H01L21/338

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L29/42376 ,  H01L29/66575

Abstract: A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.

Abstract translation: 一种T形栅极结构及其形成方法，包括提供包括至少一个上覆牺牲层的半导体衬底; 光刻地图案化覆盖至少一个牺牲层的抗蚀剂层，以蚀刻开口; 通过所述至少一个牺牲层的厚度形成所述蚀刻开口以暴露所述半导体衬底，所述蚀刻开口包括与底部相比具有较宽上部的锥形横截面; 并且用栅电极材料回填蚀刻的开口以形成栅极结构。

公开(公告)号：US06776177B2

公开(公告)日：2004-08-17

申请号：US10300829

申请日：2002-11-21

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: E04H1528

CPC classification number: E04H15/28 ,  E04H15/40

Abstract: A gardening protective shelter in umbrella shape includes a main rod, a plurality of ribs, a protective cover and a handle. The feature of the present invention is a sliding ring wraps around the main rod and is beneath a runner, a pulling rope each ties to the runner and the sliding ring respectively along the main rod and stretches out from the handle, an open ring and a close ring is at the end of the pulling ropes respectively. Users can pull two control rings to open and close the rib for easier installation and restoration.

Abstract translation: 伞形的园艺防护罩包括主杆，多个肋，保护罩和把手。 本发明的特征是滑环围绕主杆环绕，并且在滑道下方，牵引绳各自分别沿着主杆与滑块和滑环相连，并从手柄伸出，开环和 拉绳的末端分别是闭环。 用户可以拉两个控制环打开和关闭肋条，便于安装和恢复。

公开(公告)号：US06770516B2

公开(公告)日：2004-08-03

申请号：US10235253

申请日：2002-09-05

Applicant: Chung Cheng Wu ,  Shye-Lin Wu

Inventor： Chung Cheng Wu ,  Shye-Lin Wu

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/962

Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape. An anneal procedure results creation of a source/drain region of a first conductivity type in portions of the first SOI fin type shape underlying the first doped insulator layer, and creation of a source/drain region of a second conductivity type in portions of the second SOI fin type shape underlying the second doped insulator layer. Selective deposition of tungsten on exposed top surface of the source/drain regions is then employed to decrease source/drain resistance.

Abstract translation: 已经开发了形成具有N沟道器件和形成在同一SOI层中的P沟道器件的FINFET CMOS器件结构的方法。 该方法特征是形成两个平行的SOI鳍式结构，随后在SOI鳍型结构的侧面上形成栅极绝缘体，并且界定在栅极绝缘体层之间穿过SOI鳍型结构的导电栅极结构。 在第一SOI鳍型形状的暴露的顶表面上形成第一导电类型的掺杂绝缘体层，而在第二SOI鳍型形状的暴露的顶表面上形成第二导电类型的第二掺杂绝缘体层。 退火程序导致在第一掺杂绝缘体层下面的第一SOI鳍型形状的部分中产生第一导电类型的源极/漏极区域，并且在第二导电类型的部分中产生第二导电类型的源极/漏极区域 第二掺杂绝缘体层下方的SOI鳍型。 然后选择性沉积钨在源极/漏极区域的暴露的顶表面上，以降低源极/漏极电阻。

公开(公告)号：US06569729B1

公开(公告)日：2003-05-27

申请号：US10199854

申请日：2002-07-19

Applicant: Chung-Cheng Wu ,  Shye-Lin Wu

Inventor： Chung-Cheng Wu ,  Shye-Lin Wu

IPC: H01L21761

CPC classification number: H01L21/84 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823871 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L28/90

Abstract: A method of reducing the aspect ratio for dry etch processes used to form contact hole and storage node openings in composite insulator layers, to expose regions of CMOS devices used for embedded memory cell applications, has been developed. The method features formation of CMOS devices for an embedded memory cell in a recessed region of a semiconductor substrate, while peripheral, higher performing CMOS devices are formed on a non-recessed, SOI layer. Removal of a top portion of a first planarized insulator layer, only in the embedded memory cell region, allows reduction of the aspect ratio of a storage node opening formed in the bottom portion of the first planarized insulator layer. Formation of an overlying, second planarized insulator layer results in a composite insulator layer comprised of a thinned, second planarized insulator layer on the underlying first planarized insulator layer, in the peripheral CMOS device region. The thinned, second planarized insulator component of the composite insulator layer allows reduction of the aspect ratio for formation of a contact hole now defined in the composite insulator layer.

Abstract translation: 已经开发了一种减少用于在复合绝缘体层中形成接触孔和存储节点开口的干式蚀刻工艺的长宽比，以暴露用于嵌入式存储器单元应用的CMOS器件的区域的方法。 该方法的特征在于在半导体衬底的凹陷区域中为嵌入式存储器单元形成CMOS器件，而在非凹入的SOI层上形成外围更高性能的CMOS器件。 仅在嵌入的存储单元区域中去除第一平坦化绝缘体层的顶部，可以减小形成在第一平坦化绝缘体层的底部中的存储节点开口的纵横比。 上覆的第二平坦化绝缘体层的形成导致在外围CMOS器件区域中的下面的第一平坦化绝缘体层上的薄化的第二平坦化绝缘体层的复合绝缘体层。 复合绝缘体层的薄化的第二平坦化绝缘体部件允许减小用于形成现在限定在复合绝缘体层中的接触孔的纵横比。

公开(公告)号：US06548363B1

公开(公告)日：2003-04-15

申请号：US09547237

申请日：2000-04-11

Applicant: Chung-Cheng Wu ,  Bi-Ling Lin ,  Carlos Hernando Diaz

Inventor： Chung-Cheng Wu ,  Bi-Ling Lin ,  Carlos Hernando Diaz

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/7833

Abstract: A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode. There is then formed employing low energy ion implantation shallow junction source-drain extension regions adjacent to the gate electrode. There is then formed source-drain regions to complete the FET device, which exhibits attenuated drain leakage current. The present invention may be employed to fabricate complementary metal-oxide-silicon (CMOS) FET devices of either polarity with attenuated gate induced drain leakage (GIDL) current, short channel effect (SCE) and punch-through leakage current in integrated circuit microelectronics fabrications wherein low power drain is desired.

Abstract translation: 一种用于形成具有衰减栅极感应漏极漏电流的FET器件的方法。 提供了在微电子制造中使用的硅半导体衬底。 形成硅衬底场氧化物（FOX）电介质隔离区域，限定有源硅衬底器件区域。 在衬底上形成采用热氧化的氧化硅栅极氧化物绝缘层。 然后在氧化硅栅极氧化物绝缘层上形成图案化的多晶硅栅极电极层。 然后，将基板和多晶硅栅电极热氧化，以在栅电极的边缘和相邻的硅衬底区域中形成较厚的氧化硅层。 然后从与栅电极相邻的硅衬底区域中回蚀更厚的氧化硅层。 然后形成采用与栅电极相邻的低能离子注入浅结源极 - 漏极扩展区。 然后形成源极 - 漏极区以完成FET器件，其表现出衰减的漏极漏电流。 本发明可用于在集成电路微电子器件制造中制造具有衰减栅极感应漏极泄漏（GIDL）电流，短沟道效应（SCE）和穿通漏电流两种极性的互补金属氧化物 - 硅（CMOS）FET器件 其中期望低功率消耗。

公开(公告)号：US6069052A

公开(公告)日：2000-05-30

申请号：US706652

申请日：1996-10-07

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L28/84

Abstract: The present invention provides a process and a structure for increasing a capacitance of a stack capacitor. The process includes steps of: a) forming a contact hole on a silicon substrate having an oxide layer, b) forming a polysilicon contact plug of a first polysilicon layer in the contact hole; c) forming a second gibbous polysilicon layer on a surface of the contact plug, and d) forming a third polysilicon layer above the gibbous polysilicon layer and a portion of the oxide layer to form the stack capacitor, wherein the gibbous polysilicon layer increases the capacitance of the stack capacitor.

Abstract translation: 本发明提供一种用于增加堆叠电容器的电容的工艺和结构。 该方法包括以下步骤：a）在具有氧化物层的硅衬底上形成接触孔，b）在接触孔中形成第一多晶硅层的多晶硅接触插塞; c）在所述接触插塞的表面上形成第二起绒多晶硅层，以及d）在所述起伏多晶硅层上方形成第三多晶硅层和所述氧化物层的一部分以形成所述堆叠电容器，其中所述起伏多晶硅层增加所述电容 的堆叠电容器。