公开(公告)号：US06259134B1

公开(公告)日：2001-07-10

申请号：US09112978

申请日：1998-07-09

Applicant: Gehan A. J Amaratunga ,  Florin Udrea

Inventor： Gehan A. J Amaratunga ,  Florin Udrea

IPC: H01L2976

CPC classification number: H01L29/749 ,  H01L27/0716 ,  H01L29/42308 ,  H01L29/7455

Abstract: A MOS-controllable power semiconductor trench device has a gate in the form of a trench which extends through a region of p type silicon into an n type region of low conductivity. A discontinous buried p layer below the bottom of the trench forms part of a thyristor which in operation is triggered into conduction by conduction of a PIN diode which is produced when an accumulation layer is formed in the n type region adjacent to the trench under the action of an on-state gate signal. The device has a high on-state conductivity and is protected against high voltage breakdown in its off-state by the presence of the buried layer. An off-state gate signal causes removal of the accumulation layer and conduction of the PIN diode and the thyristor ceases in safe, reliable and rapid manner.

Abstract translation: MOS可控功率半导体沟槽器件具有沟槽形式的栅极，其延伸穿过p型硅的区域到n型低导电区域。 在沟槽底部下方的不连续埋层p层形成晶闸管的一部分，晶闸管在工作中通过PIN二极管的导通而被触发导通，该PIN二极管是当在作用下邻近沟槽的n型区域中形成蓄积层时产生的 的状态门信号。 器件具有高的导通状态，并且通过存在掩埋层来保护其处于其断开状态的高压击穿。 截止状态的栅极信号使安全，可靠和快速地停止积聚层，PIN二极管和晶闸管的导通停止。

公开(公告)号：US6111289A

公开(公告)日：2000-08-29

申请号：US289615

申请日：1999-04-12

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L29/772

CPC classification number: H01L29/861 ,  H01L29/0634 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/41758

Abstract: A semiconductor device has first and second electrical terminals. The device comprises at least one n/p or p/n first junction adjacent the first terminal, and at least one of the other of a p/n or n/p second junction adjacent the second terminal. It also has at least one n/p or p/n junction disposed between the first and second junctions and arranged to be transverse thereto, and at least one gate terminal in contact with the p or n doped region of the first junction or the n or p doped region of the second junction.

Abstract translation: 半导体器件具有第一和第二电端子。 该装置包括与第一端子相邻的至少一个n / p或p / n第一结，以及与第二端子相邻的p / n或n / p第二接头中的至少一个。 它还具有至少一个n / p或p / n结，该n / p或p / n结设置在第一和第二结之间并且布置成横向于其，并且至少一个栅极端子与第一结的p或n掺杂区域或n 或第二结的p掺杂区域。

公开(公告)号：US08970016B2

公开(公告)日：2015-03-03

申请号：US13486614

申请日：2012-06-01

Applicant: Marina Antoniou ,  Florin Udrea ,  Elizabeth Kho Ching Tee ,  Steven John Pilkington ,  Deb Kumar Pal ,  Alexander Dietrich Hölke

Inventor： Marina Antoniou ,  Florin Udrea ,  Elizabeth Kho Ching Tee ,  Steven John Pilkington ,  Deb Kumar Pal ,  Alexander Dietrich Hölke

IPC: H01L29/02

CPC classification number: H01L29/402 ,  H01L21/761 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/7823 ,  H01L29/861

Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure.

Abstract translation: 一种包括p或p +掺杂部分和通过半导体漂移部分从p或p +掺杂部分分离的n或n +掺杂部分的半导体器件。 该装置还包括邻近漂移部分设置的至少一个终端部分。 所述至少一个终端部分包括超结结构。

公开(公告)号：US08410560B2

公开(公告)日：2013-04-02

申请号：US12691104

申请日：2010-01-21

Applicant: Syed Zeeshan Ali ,  Florin Udrea ,  Julian William Gardner

Inventor： Syed Zeeshan Ali ,  Florin Udrea ,  Julian William Gardner

IPC: H01L27/14 ,  H01L21/00

CPC classification number: H05B3/267 ,  Y10T29/49083

Abstract: A micro-hotplate is provided in the form of a device comprising a sensor and one or more resistive heaters within the micro-hotplate arranged to heat the sensor. Furthermore a controller is provided for applying a bidirectional drive current to at least one of the heaters to reduce electromigration. The controller also serves to drive the heater at a substantially constant temperature.

Abstract translation: 提供微电子装置的形式包括传感器和微电热板内的一个或多个电阻加热器，其布置成加热传感器。 此外，提供了一种控制器，用于向至少一个加热器施加双向驱动电流以减少电迁移。 控制器还用于以基本恒定的温度驱动加热器。

公开(公告)号：US20120267532A1

公开(公告)日：2012-10-25

申请号：US13466626

申请日：2012-05-08

Applicant: Florin UDREA ,  Julian GARDNER ,  Syed Zeeshan ALI ,  Mohamed Foysol CHOWDHURY ,  Ilie POENARU

Inventor： Florin UDREA ,  Julian GARDNER ,  Syed Zeeshan ALI ,  Mohamed Foysol CHOWDHURY ,  Ilie POENARU

IPC: G01N21/61 ,  G21K5/02 ,  H01L21/02 ,  B82Y15/00

CPC classification number: H05B3/267 ,  G01J3/108 ,  H05B2203/032

Abstract: An IR source in the form of a micro-hotplate device including a CMOS metal layer made of at least one layer of embedded on a dielectric membrane supported by a silicon substrate. The device is formed in a CMOS process followed by a back etching step. The IR source also can be in the form of an array of small membranes—closely packed as a result of the use of the deep reactive ion etching technique and having better mechanical stability due to the small size of each membrane while maintaining the same total IR emission level. SOI technology can be used to allow high ambient temperature and allow the integration of a temperature sensor, preferably in the form of a diode or a bipolar transistor right below the IR source.

Abstract translation: 微电子装置形式的IR源，其包括由至少一层嵌入在由硅衬底支撑的电介质膜上的CMOS金属层。 该器件以CMOS工艺形成，随后是背蚀刻步骤。 IR源也可以是由于使用深反应离子蚀刻技术而紧密堆积的小膜阵列的形式，并且由于每个膜的小尺寸而具有更好的机械稳定性，同时保持相同的总IR 排放水平。 可以使用SOI技术来允许高环境温度并且允许温度传感器的集成，优选地在IR源的正下方的二极管或双极晶体管的形式。

公开(公告)号：US20120098082A1

公开(公告)日：2012-04-26

申请号：US13222249

申请日：2011-08-31

Applicant: Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

Inventor： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

IPC: H01L29/872 ,  H01L21/329

CPC classification number: H01L29/66143 ,  H01L21/22 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/872 ,  H01L29/8725

Abstract: A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

Abstract translation: 半导体整流器包括具有第一类导电性的半导体衬底。 形成在基板上的第一层具有第一类导电性，并且比衬底更轻掺杂。 在基板上形成具有第二导电类型的第二层，并且金属层设置在第二层上。 第二层被轻掺杂，使得在金属层和第二层之间形成肖特基接触。 第一电极形成在金属层的上方，第二电极形成在基板的背面。

公开(公告)号：US07994569B2

公开(公告)日：2011-08-09

申请号：US12186966

申请日：2008-08-06

Applicant: Florin Udrea ,  Chih-Wei Hsu

Inventor： Florin Udrea ,  Chih-Wei Hsu

IPC: H01L29/76

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: A bipolar high voltage/power semiconductor device having a low voltage terminal and a high voltage terminal is disclosed. The bipolar high voltage/power semiconductor is a vertical insulated gate bipolar transistor with injection efficiency adjustment formed by highly doped n+ islands in a p+ anode layer. The device has a vertical drift region of a first conductivity type and having vertical first and second ends. In one example, a region of the second conductivity type is provided at the second end of the vertical drift region connected directly to the vertical high voltage terminal. In another example, a vertical buffer region of the first conductivity type is provided at the vertical second end of the vertical drift region and a vertical region of a second conductivity type is provided on the other side of the vertical buffer region and connected to the vertical high voltage terminal. A plurality of electrically floating lateral island regions are provided within the vertical drift region at or towards the vertical second end of the vertical drift region, the plurality of electrically floating lateral island regions being of the first conductivity type and being more highly doped than the drift region.

Abstract translation: 公开了一种具有低电压端子和高电压端子的双极型高压/功率半导体器件。 双极性高压/功率半导体是垂直绝缘栅双极晶体管，其具有由p +阳极层中的高掺杂n +岛形成的注入效率调节。 该器件具有第一导电类型的垂直漂移区，并具有垂直的第一和第二端。 在一个示例中，第二导电类型的区域设置在直接连接到垂直高压端子的垂直漂移区域的第二端。 在另一示例中，第一导电类型的垂直缓冲区域设置在垂直漂移区域的垂直第二端，并且第二导电类型的垂直区域设置在垂直缓冲区域的另一侧并连接到垂直方向 高压端子。 多个电浮动横向岛区域设置在垂直漂移区域内或垂直于垂直漂移区域的垂直第二端处，多个电浮动横向岛区域是第一导电类型并且比漂移更高的掺杂 地区。

公开(公告)号：US07691694B2

公开(公告)日：2010-04-06

申请号：US11785276

申请日：2007-04-17

Applicant: Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L21/337

CPC classification number: H01L29/1608 ,  H01L29/66068 ,  H01L29/8083 ,  Y10S438/931

Abstract: A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first channel layer adjacent to the first gate layer on the substrate; a first source layer connecting to the first channel layer electrically; a second gate layer adjacent to the first channel layer to sandwich the first channel layer; a second channel layer adjacent to the second gate layer to sandwich the second gate layer; a third gate layer adjacent to the second channel layer to sandwich the second channel layer; and a second source layer connecting to the second channel layer electrically.

Abstract translation: 碳化硅半导体器件包括衬底和结场效应晶体管。 晶体管包括：设置在基板上的第一半导体层; 设置在所述第一半导体层的表面上的第一栅极层; 与所述基板上的所述第一栅极层相邻的第一沟道层; 电连接到第一沟道层的第一源极层; 与所述第一沟道层相邻以夹住所述第一沟道层的第二栅极层; 与所述第二栅极层相邻以夹住所述第二栅极层的第二沟道层; 与所述第二沟道层相邻以夹住所述第二沟道层的第三栅极层; 以及电连接到第二沟道层的第二源极层。

公开(公告)号：US20100032712A1

公开(公告)日：2010-02-11

申请号：US12186231

申请日：2008-08-05

Applicant: Florin UDREA ,  Vasantha PATHIRANA ,  Tanya TRAJKOVIC ,  Nishad UDUGAMPOLA

Inventor： Florin UDREA ,  Vasantha PATHIRANA ,  Tanya TRAJKOVIC ,  Nishad UDUGAMPOLA

IPC: H01L29/739 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/0657 ,  H01L29/0839 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7394 ,  H01L29/7824

Abstract: A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.

Abstract translation: 功率半导体器件具有顶表面和相对的底表面，其下面的一部分是半导体衬底的厚部分。 装置的漂移区域的至少一部分具有没有或仅有半导体衬底的薄的部分位于其下方。 顶表面具有高电压端子和与其连接的低电压端子，以允许跨越漂移区域横向施加电压。 在顶表面上设置至少两个MOS（金属氧化物半导体）栅极。 器件在其顶表面处具有至少一个相对高度掺杂的区域，其在所述第一和第二MOS栅极之间延伸并与之接触。 该器件具有改进的防止寄生晶体管触发或闩锁的保护，而不会导致导通电压降或开关速度受损。

公开(公告)号：US07605446B2

公开(公告)日：2009-10-20

申请号：US11486377

申请日：2006-07-14

Applicant: Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

IPC: H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/58

CPC classification number: H01L29/7393 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/7394 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.

Abstract translation: 双极高压/功率半导体器件具有分别具有与其不同导电类型的端部区域相邻的漂移区域。 提供高低压端子。 还提供了第一绝缘栅极端子和第二绝缘栅极端子。 一个或多个驱动电路为第一和第二绝缘栅极端子提供适当的电压，以允许在与第一方向相反的第一方向或第二方向上的电流传导。