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公开(公告)号：US12015096B2
公开(公告)日：2024-06-18
申请号：US16807957
申请日：2020-03-03
发明人： Henning Feick
IPC分类号： H01L31/103 , H01L27/144 , H01L31/02 , H01L31/0224
CPC分类号： H01L31/103 , H01L27/1443 , H01L31/02019 , H01L31/0224
摘要： According to an embodiment, a time of flight sensor device includes: a semiconductor substrate having a conversion region to convert an electromagnetic signal into photo-generated charge carriers, and including a substrate doping region having a n-doping type. The substrate doping region extends from a first main surface region of the semiconductor substrate into the semiconductor substrate. The semiconductor substrate has a p doped region adjacent to the substrate doping region. The substrate doping region at least partially forms the conversion region in the semiconductor substrate. A readout node arranged in the semiconductor substrate within the substrate doping region and having the n-doping type is configured to readout the photo generated charge carriers. A control electrode is arranged in the substrate doping region of the semiconductor substrate and in the substrate doping region and has a p-doping type.
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公开(公告)号：US12014981B2
公开(公告)日：2024-06-18
申请号：US17662790
申请日：2022-05-10
发明人： Marcus Nuebling , Mathias Racki
IPC分类号： H01L23/522 , H01L27/06 , H01L49/02
CPC分类号： H01L23/5227 , H01L23/5225 , H01L27/0629 , H01L28/10
摘要： An example circuit includes a coil structure located on at least a first layer of an integrated circuit (IC); and a circuit component comprising conduction paths. The conduction paths are located on one or more layers separate from the first layer and the first layer and the one or more layers form parallel planes. The conduction paths of the circuit component are oriented to avoid eddy currents in the conduction paths caused by an electric current through the coil structure and form a patterned shield. At least some of the conduction paths define an area, and the coil structure is located within the defined area.
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公开(公告)号：US12014964B2
公开(公告)日：2024-06-18
申请号：US17986306
申请日：2022-11-14
发明人： Eung San Cho , Tomasz Naeve , Petteri Palm
IPC分类号： H01L23/14 , H01L23/482 , H01L23/498
CPC分类号： H01L23/142 , H01L23/4827 , H01L23/49827
摘要： A semiconductor package includes: an electrically insulating core and an electrically conductive first via extending through a periphery region of the core, the core having glass fibres interwoven with epoxy material and one or more regions where the glass fibres are exposed from the epoxy material; a power semiconductor die embedded in an opening in the core and having a first load terminal bond pad which faces a same direction as a first side of the core, a second load terminal bond pad which faces a same direction as a second side of the core, and a control terminal bond pad; a resin that encases the power semiconductor die; a first contact pad plated on the first via at the second side of the core; and a second contact pad plated on the first load terminal bond pad of the power semiconductor die at the first side of the core.
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公开(公告)号：US12014963B2
公开(公告)日：2024-06-18
申请号：US17362088
申请日：2021-06-29
发明人： Tomas Manuel Reiter , Peter Bayer , Christoph Koch
IPC分类号： H01L23/053 , H01L23/14 , H01L23/495 , H01L23/528 , H05K3/40 , H05K3/32
CPC分类号： H01L23/053 , H01L23/145 , H01L23/49503 , H01L23/5286 , H05K3/40 , H05K3/32
摘要： A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions. Methods of producing the power semiconductor module and power electronic assemblies that incorporate the power semiconductor module are also described.
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55.发明授权公开(公告)号：US12013383B2
公开(公告)日：2024-06-18
申请号：US17645627
申请日：2021-12-22
CPC分类号： G01N33/0036 , G01N27/308
摘要： A gas sensing device comprises a sensing unit for sensing a target gas, the sensing unit comprising a carbon-based sensing layer which is sensitive to the target gas. The gas sensing device further comprises a controller unit for monitoring an exposure of the sensing layer to the target gas. The controller unit further initializes a recovery sequence for the sensing unit depending on an exposure of the sensing unit to the target gas. Further, the gas sensing device comprises a heating electrode for heating the sensing layer during the recovery sequence.
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公开(公告)号：US20240195788A1
公开(公告)日：2024-06-13
申请号：US18065424
申请日：2022-12-13
CPC分类号： H04L63/0428 , H04L9/0861 , H04L9/14
摘要： A network node may receive a control plane message. The control plane message may include an indication that the control plane message is a control plane message, an indication that the control plane message is associated with security, an indication of a security key to be associated with a secure zone (SZ) of an in-vehicle communication network, and an indication of a freshness value. The network node may perform a cryptographic operation for a data plane message associated with the SZ using the security key.
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公开(公告)号：US20240194444A1
公开(公告)日：2024-06-13
申请号：US18524043
申请日：2023-11-30
发明人： Moriz Jelinek , Axel König , Bernhard Leitl
IPC分类号： H01J37/317 , H01J37/304
CPC分类号： H01J37/3171 , H01J37/304 , H01J2237/24405 , H01J2237/24528 , H01J2237/24535 , H01J2237/31703
摘要： An ion beam current measurement device includes a first Faraday cup having a first ion beam entrance slit of a first width W1. The first Faraday cup is configured to generate a first current signal. The device further includes a second Faraday cup having a second ion beam entrance slit of a second width W2. The second Faraday cup is configured to generate a second current signal. The slit widths are designed such that W2 is greater than W1.
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公开(公告)号：US12010215B2
公开(公告)日：2024-06-11
申请号：US17674015
申请日：2022-02-17
发明人： Martin Schlaeffer
IPC分类号： H04L9/06 , G06F12/1018 , G06F12/14 , H04L9/32
CPC分类号： H04L9/0643 , G06F12/1018 , G06F12/1408 , H04L9/3239
摘要： Determining hash values based on at least two types of hash functions, utilizing a memory that is arranged to store at least one state to be used to determine hash values pursuant to a SHA-3 function, wherein hash values pursuant to any of a SHA-2 function or a SHA-1 function are determined based on the state.
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59.发明公开公开(公告)号：US20240183883A1
公开(公告)日：2024-06-06
申请号：US18061001
申请日：2022-12-02
CPC分类号： G01R15/181 , G01R27/28
摘要： Circuits, devices and systems that include a low voltage test for common mode transient immunity (CMTI). The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common mode transient rejection, the first signal path should be the same as the second signal path. Differences in the resistance, inductance, and capacitance between the two signal paths may result in common mode noise being measured as a differential signal at the output terminals. Devices according to the techniques of this disclosure are configured to enter a test mode to conduct a low voltage test that outputs a measurement of CMTI at any phase of production or field use.
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公开(公告)号：US20240182297A1
公开(公告)日：2024-06-06
申请号：US18519897
申请日：2023-11-27
CPC分类号： B81C1/00285 , B81B7/0029 , B81B2201/0257 , B81C2201/0132 , H04R1/023 , H04R2201/003 , H04R2201/029
摘要： A method for manufacturing a micromechanical environmental barrier chip includes providing a substrate having a first surface and an opposite second surface, depositing a material layer having a different etch characteristic than the substrate onto the first surface, creating a microstructured micromechanical environmental barrier structure on top of the material layer by applying a microstructuring process, applying an anisotropic etching process comprising at least one etching step for anisotropically etching from the second surface towards the first surface to create at least a cavity underneath the micromechanical environmental barrier structure, the cavity extending between the second surface and the material layer, and removing the material layer underneath the micromechanical environmental barrier structure to expose the environmental barrier structure.
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