利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

149 条记录 (耗时 0.02 秒)

    Method for depositing doped amorphous or polycrystalline silicon on a substrate
    52.
    发明授权
    Method for depositing doped amorphous or polycrystalline silicon on a substrate 失效
    在衬底上沉积掺杂的非晶或多晶硅的方法

    公开(公告)号：US5789030A

    公开(公告)日：1998-08-04

    申请号：US618281

    申请日：1996-03-18

    申请人： J. Brett Rolfson

    发明人： J. Brett Rolfson

    IPC分类号： C23C16/02 ,  C23C16/24 ,  H01L21/02 ,  H01L21/205 ,  B05D3/04 ,  B05D3/06

    CPC分类号： H01L28/60 ,  C23C16/0218 ,  C23C16/24 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  Y10S148/122 ,  Y10S438/925

    摘要： A method for forming an in-situ doped amorphous or polycrystalline silicon thin film on a substrate is provided. The method includes placing the substrate in a reaction chamber of a CVD reactor and introducing a silicon gas species into the reaction chamber. The flow of the silicon gas species is continued for a time period sufficient to dehydrate the substrate and form a thin layer of silicon. Following formation of the thin layer of silicon, a dopant gas species is introduced into the reaction chamber and continued with the flow of the silicon gas species to form the doped silicon thin film. In an illustrative embodiment a phosphorus doped amorphous silicon thin film for a cell plate of a semiconductor capacitor is formed in a LPCVD reactor.

    摘要翻译： 提供了一种在衬底上形成原位掺杂的非晶或多晶硅薄膜的方法。 该方法包括将衬底放置在CVD反应器的反应室中并将硅气体物质引入反应室中。 硅气体物质的流动持续一段足以使基底脱水并形成薄的硅层的时间。 在形成薄层的硅之后，将掺杂气体物质引入到反应室中并随着硅气体种类的流动继续以形成掺杂的硅薄膜。 在说明性实施例中，在LPCVD反应器中形成用于半导体电容器的单元板的磷掺杂非晶硅薄膜。

    Method of making masks for phase shifting lithography to avoid phase conflicts
    53.
    发明授权
    Method of making masks for phase shifting lithography to avoid phase conflicts 失效
    制作相移光刻掩模以避免相位冲突的方法

    公开(公告)号：US5468578A

    公开(公告)日：1995-11-21

    申请号：US312408

    申请日：1994-09-26

    申请人： J. Brett Rolfson

    发明人： J. Brett Rolfson

    IPC分类号： G03F1/30 ,  H01L21/027 ,  G03F9/00

    CPC分类号： G03F1/30

    摘要： An improved method of fabricating a phase shifting mask suitable for semiconductor manufacture includes the steps of identifying phase conflict areas in a desired mask pattern and forming phase shift bands in the phase conflict areas. Phase conflict areas occur in transparent areas of the mask pattern which are in close proximity to one another and which have the same phase. More specifically, the method of the invention includes the steps of: depositing an opaque layer (i.e., chrome) on a transparent substrate, etching openings in the opaque layer to form a pattern of transparent areas and opaque areas, connecting adjacent transparent areas together in the phase conflict areas, and forming phase shift areas in every other transparent area and in the connecting areas.

    摘要翻译： 制造适合于半导体制造的相移掩模的改进方法包括以下步骤：识别所需掩模图案中的相冲突区域并在相冲突区域中形成相移带。 相位冲突区域出现在彼此相邻并具有相同相位的掩模图案的透明区域中。 更具体地说，本发明的方法包括以下步骤：将不透明层（即铬）沉积在透明基底上，蚀刻不透明层中的开口以形成透明区域和不透明区域的图案，将邻近的透明区域连接在一起 相冲突区域，并在每个其他透明区域和连接区域中形成相移区域。

    Etch stop useful in avoiding substrate pitting with poly buffered locos
    54.
    发明授权
    Etch stop useful in avoiding substrate pitting with poly buffered locos 失效
    蚀刻停止可用于避免基底点蚀与多缓冲区域

    公开(公告)号：US5358892A

    公开(公告)日：1994-10-25

    申请号：US017100

    申请日：1993-02-11

    申请人： J. Brett Rolfson

    发明人： J. Brett Rolfson

    IPC分类号： H01L21/32 ,  H01L21/3213 ,  H01L21/76

    CPC分类号： H01L21/32 ,  H01L21/32134 ,  Y10S148/156 ,  Y10S438/954

    摘要： Active regions on a semiconductor substrate are isolated, whereby an Oxide/Nitride/Oxide sandwich is disposed on a substrate, and a polysilicon layer and a nitride layer are also disposed thereon. The Oxide/Nitride/Oxide sandwich substantially inhibits "pitting" of the substrate when the polysilicon layer is removed.Method of preventing "pitting" of an underlying substrate through the use of a nitride (or other HF-resistant material) disposed beneath the polysilicon layer of a Poly Buffered LOCOS stack.

    摘要翻译： 隔离半导体衬底上的有源区，由此在衬底上设置氧化物/氮化物/氧化物夹层物，并且还在其上设置多晶硅层和氮化物层。 当去除多晶硅层时，氧化物/氮化物/氧化物夹层基本上抑制衬底的“点蚀”。 通过使用设置在多缓冲LOCOS堆叠的多晶硅层下面的氮化物（或其他抗HF材料）来防止下层衬底“点蚀”的方法。

    Method to form self-aligned gate structures and focus rings
    55.
    发明授权
    Method to form self-aligned gate structures and focus rings 失效
    形成自对准栅极结构和聚焦环的方法

    公开(公告)号：US5259799A

    公开(公告)日：1993-11-09

    申请号：US977477

    申请日：1992-11-17

    申请人： Trung T. Doan ,  Tyler A. Lowrey ,  David A. Cathey ,  J. Brett Rolfson

    发明人： Trung T. Doan ,  Tyler A. Lowrey ,  David A. Cathey ,  J. Brett Rolfson

    IPC分类号： H01J9/02 ,  H01J9/04

    CPC分类号： H01J9/025 ,  H01J2209/0226 ,  H01J2329/00

    摘要： A selective etching and chemical mechanical planarization process for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a first conformal layer, iii) deposited with a conductive material layer, iv) deposited with a second conformal insulating layer, v) deposited with a focus electrode ring material layer, vi) optionally deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose a portion of the second conformal layer, viii) etched to form a self-aligned gate and focus ring, and thereby expose the emitter tip, afterwhich xi) the emitter tip may be coated with a low work function material.

    摘要翻译： 用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极和聚焦环结构的选择性蚀刻和化学机械平面化工艺，其中发射尖端i）可选地通过氧化锐化，ii）沉积有第一 保留层，iii）沉积有导电材料层，iv）沉积有第二共形绝缘层，v）沉积有焦点电极环材料层，vi）任选地沉积有缓冲材料，vii）用化学机械平面化 （CMP）步骤，以暴露第二共形层的一部分，viii）蚀刻以形成自对准栅极和聚焦环，从而暴露发射极尖端，之后xi）发射极尖端可以被涂覆有低功函数 材料。

    Method to form high aspect ratio supports (spacers) for field emission display using micro-saw technology
    57.
    发明授权
    Method to form high aspect ratio supports (spacers) for field emission display using micro-saw technology 失效
    使用微锯技术形成用于场发射显示的高纵横比支撑（间隔物）的方法

    公开(公告)号：US5205770A

    公开(公告)日：1993-04-27

    申请号：US851036

    申请日：1992-03-12

    申请人： Tyler A. Lowrey ,  Trung T. Doan ,  David A. Cathey ,  J. Brett Rolfson

    发明人： Tyler A. Lowrey ,  Trung T. Doan ,  David A. Cathey ,  J. Brett Rolfson

    IPC分类号： H01J9/24 ,  H01J29/02 ,  H01J31/12

    CPC分类号： H01J9/242 ,  H01J31/123 ,  H01J2329/8625

    摘要： Fabrication of spacer supports for use in field emitter displays through a process which involves 1) forming a mold for the spacers in a substrate through the use of micro-saw technology, 2) filling the mold with a material that is selectively etchable with respect to the mold, 3) optionally, planarizing the excess material to the level of the mold using chemical mechanical planarization, 4) attaching the filled mold to one of the electrode plates of the field emitter display, and 5) etching away (removing) the mold, after which 6) the plate can be aligned with its complementary electrode plate, and 7) a vacuum formed.

    摘要翻译： 通过一种方法制造用于场致发射显示器的间隔支架，该方法涉及1）通过使用微锯技术在衬底中形成用于衬垫的模具，2）用相对于 模具，3）任选地，使用化学机械平面化将多余材料平坦化到模具的水平面; 4）将填充的模具附接到场致发射体显示器的电极板之一，以及5）蚀刻（去除）模具 ，之后6）板可以与其互补电极板对准，并且7）形成真空。

    Method to form self-aligned gate structures and focus rings
    58.
    发明授权
    Method to form self-aligned gate structures and focus rings 失效
    形成自对准栅极结构和聚焦环的方法

    公开(公告)号：US5186670A

    公开(公告)日：1993-02-16

    申请号：US844369

    申请日：1992-03-02

    申请人： Trung T. Doan ,  Tyler A. Lowrey ,  David A. Cathey ,  J. Brett Rolfson

    发明人： Trung T. Doan ,  Tyler A. Lowrey ,  David A. Cathey ,  J. Brett Rolfson

    IPC分类号： H01J9/02

    CPC分类号： H01J9/025 ,  H01J2209/0226 ,  H01J2329/00

    摘要： A selective etching and chemical mechanical planarization process for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a first conformal layer, iii) deposited with a conductive material layer, iv) deposited with a second conformal insulating layer, v) deposited with a focus electrode ring material layer, vi) optionally deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose a portion of the second conformal layer, viii) etched to form a self-aligned gate and focus ring, and thereby expose the emitter tip, afterwhich xi) the emitter tip may be coated with a low work function material.

    Multi-layer, attenuated phase-shifting mask
    59.
    发明授权
    Multi-layer, attenuated phase-shifting mask 失效
    多层衰减相移掩模

    公开(公告)号：US07838183B2

    公开(公告)日：2010-11-23

    申请号：US12581455

    申请日：2009-10-19

    申请人： J. Brett Rolfson

    发明人： J. Brett Rolfson

    IPC分类号： G03F1/00

    CPC分类号： G03F1/32 ,  G03F1/29

    摘要： The present invention provides an attenuated phase shift mask (“APSM”) that, in each embodiment, includes completely transmissive regions sized and shaped to define desired semiconductor device features, slightly attenuated regions at the edges of the completely transmissive regions corresponding to isolated device features, highly attenuated regions at the edges of completely transmissive regions corresponding to closely spaced or nested device features, and completely opaque areas where it is desirable to block transmission of all radiation through the APSM. The present invention further provides methods for fabricating the APSMs according to the present invention.

    摘要翻译： 本发明提供了衰减相移掩模（“APSM”），其在每个实施例中包括尺寸和形状以确定期望的半导体器件特征的完全透射区域，在完全透射区域的边缘处对应于隔离的器件特征的略微衰减的区域 在完全透射区域的边缘处的高度衰减的区域对应于紧密间隔或嵌套的器件特征，以及完全不透明的区域，其中期望阻止通过APSM的所有辐射的透射。 本发明还提供了制造根据本发明的APSM的方法。