公开(公告)号：US20100234741A1

公开(公告)日：2010-09-16

申请号：US12520246

申请日：2008-08-29

Applicant: Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

Inventor： Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

IPC: A61B5/0205 ,  A61B5/024

CPC classification number: G08B21/06 ,  A61B5/0205 ,  A61B5/0402 ,  A61B5/0507 ,  A61B5/1102 ,  A61B5/7455 ,  A61B2503/22

Abstract: The present invention relates to a drowsiness detection method. A heartbeat signal and a breathing signal are detected by exploiting together a scheme and an optical system scheme. The detected signals are applied to respective amplification units, noise signals are eliminated from the detected signals, and noise-free signals are amplified. The amplified signals are applied to a central processing unit, signal processing is processed on the signals, and processed signals are combined. The combined signal is counted, and a warning sound, voice message or vibration is output in a case where a value, obtained by subtracting a counted output value monitored one minute before a current time, from a counted output value monitored two minutes before the current time, falls within a detection range and where, with a passage of time, the value falling within the detection range is successively detected from two to ten times.

Abstract translation: 本发明涉及一种嗜睡检测方法。 通过一起利用方案和光学系统方案来检测心跳信号和呼吸信号。 检测到的信号被施加到各个放大单元，从检测到的信号中消除噪声信号，并且无噪声信号被放大。 将放大的信号施加到中央处理单元，对信号进行信号处理，并且处理的信号被组合。 对组合的信号进行计数，并且在通过从当前时间之前1分钟监视的计数输出值减去得到的值从在当前的两分钟前监视的计数输出值得到的值的情况下输出警告声音，语音消息或振动 时间落在检测范围内，并且随着时间的流逝，落在检测范围内的值被连续地检测到两到十次。

公开(公告)号：US07750714B2

公开(公告)日：2010-07-06

申请号：US12136878

申请日：2008-06-11

Applicant: Mi Hye Kim ,  Jae Jin Lee

Inventor： Mi Hye Kim ,  Jae Jin Lee

IPC: H03K3/00

CPC classification number: G11C5/147 ,  G11C5/143 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/00384 ,  H03K2005/0013 ,  H03K2005/00208

Abstract: A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes an input potential detection unit outputting a detection signal in response to a level of an input signal, an input buffer buffering the input signal, and an output path control unit that receives the output signal of the input buffer and the detection signal of the input potential detection unit and outputs an output driving signal in response to the level of the detection signal.

Abstract translation: 半导体器件最小化输入缓冲器的输出信号偏斜的产生，从而稳定半导体器件的操作。 半导体集成电路包括输入电位检测单元，其响应于输入信号的电平，缓冲输入信号的输入缓冲器和接收输入缓冲器的输出信号和检测的输出路径控制单元输出检测信号 信号，并且响应于检测信号的电平而输出输出驱动信号。

公开(公告)号：US07586801B2

公开(公告)日：2009-09-08

申请号：US12072548

申请日：2008-02-26

Applicant: Chang-Ho Do ,  Jae-Jin Lee

Inventor： Chang-Ho Do ,  Jae-Jin Lee

IPC: G11C11/00

CPC classification number: G11C29/26 ,  G11C8/16

Abstract: A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a parallel I/O data communication with the ports; a global data bus configured to transmit a signal between the banks and the ports; a test mode determiner configured to determine an operation mode of the semiconductor memory device by generating a test mode enable signal in response to a test mode control signal; a test I/O controller configured to transmit and receive a test signal with the ports in response to the test mode enable signal during a port test mode; and a plurality of selectors, each of which is configured to receive the test signal output from the corresponding port in series and feedback the test signal to the corresponding port.

Abstract translation: 半导体存储器件包括：多个端口，被配置为执行与外部设备的串行输入/输出（I / O）数据通信; 配置为执行与所述端口的并行I / O数据通信的多个存储体; 全局数据总线，被配置为在所述存储体和所述端口之间传输信号; 测试模式确定器，被配置为通过响应于测试模式控制信号产生测试模式使能信号来确定半导体存储器件的操作模式; 测试I / O控制器，被配置为在端口测试模式期间响应于测试模式使能信号在端口上发送和接收测试信号; 以及多个选择器，每个选择器被配置为从串行的相应端口接收输出的测试信号，并将测试信号反馈到相应的端口。

公开(公告)号：US07443932B2

公开(公告)日：2008-10-28

申请号：US10747312

申请日：2003-12-30

Applicant: Hyun-soo Park ,  Jae-jin Lee ,  Jae-seong Shim ,  You-pyo Hong ,  Ju-han Bae ,  Jae-hoon Seo

Inventor： Hyun-soo Park ,  Jae-jin Lee ,  Jae-seong Shim ,  You-pyo Hong ,  Ju-han Bae ,  Jae-hoon Seo

IPC: H03D1/00

CPC classification number: G11B20/10203 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10212 ,  G11B20/10296 ,  G11B20/10425

Abstract: A method and an apparatus which adjusts a signal read from an optical disc in order to obtain stable binary data. The signal adjustment method comprises (a) detecting a period of an input signal of a predetermined code; (b) determining whether the detected period is smaller than a predetermined value; and (c) if the detected period is determined to be smaller than the predetermined value, adjusting the input signal so that its period equals the predetermined value, and outputting the input signal. The signal adjustment method and apparatus of the present invention reduce errors and improve system performance, when a signal input to the binary processor does not meet its code feature.

Abstract translation: 调整从光盘读取的信号以获得稳定的二进制数据的方法和装置。 信号调整方法包括：（a）检测预定码的输入信号的周期; （b）确定所检测的周期是否小于预定值; 以及（c）如果所述检测周期被确定为小于所述预定值，则调整所述输入信号使其周期等于所述预定值，并输出所述输入信号。 当输入到二进制处理器的信号不符合其代码特征时，本发明的信号调整方法和装置减少误差并提高系统性能。

公开(公告)号：US20080106451A1

公开(公告)日：2008-05-08

申请号：US11819795

申请日：2007-06-29

Applicant: Chun-Seok Jeong ,  Jae-Jin Lee

Inventor： Chun-Seok Jeong ,  Jae-Jin Lee

IPC: H03M1/12 ,  G01K1/00

CPC classification number: G01K7/015 ,  G01K7/425 ,  H03M1/005 ,  H03M1/0863 ,  H03M1/109 ,  H03M1/40 ,  H03M1/46

Abstract: An On Die Thermal Sensor (ODTS) of a semiconductor memory device includes: a temperature detector for detecting an internal temperature of the semiconductor memory device to generate a temperature voltage corresponding to the detected internal temperature; a tracking ADC for outputting a digital code by comparing the temperature voltage with a tracking voltage and performing a counting operation to the result of comparison; and an operation controller for controlling operations of the temperature detector and the analog-to-digital converter, wherein the tracking ADC performs the counting operation using a first tracking scheme having a relatively large unit variation width of the digital code value during an initial tracking period and a second tracking scheme having a relatively small unit variation width of the digital code value after the initial tracking period.

Abstract translation: 半导体存储器件的散热片传感器（ODTS）包括：温度检测器，用于检测半导体存储器件的内部温度以产生对应于检测到的内部温度的温度电压; 跟踪ADC，用于通过将温度电压与跟踪电压进行比较来输出数字代码，并对比较结果执行计数操作; 以及用于控制温度检测器和模数转换器的操作的操作控制器，其中跟踪ADC使用在初始跟踪周期期间具有数字码值的相对大的单位变化宽度的第一跟踪方案来执行计数操作 以及在初始跟踪周期之后具有数字码值的相对小的单位变化宽度的第二跟踪方案。

公开(公告)号：US07310268B2

公开(公告)日：2007-12-18

申请号：US11115301

申请日：2005-04-27

Applicant: Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

Inventor： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/0408 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7881

Abstract: A float gate memory device comprises a bottom word line, a float channel layer formed on the bottom word line and kept at a floating state, a float gate, and a top word line formed on the float gate in parallel with the bottom word line. In the float gate formed on the float channel, data are stored. Here, data are written in the float gate depending on levels of the bottom word line and the top word line, and different channel resistances are induced to the float channel depending on polarity states of charges stored in the float gate, so that data are read. As a result, in the float gate memory device, a retention characteristic is improved, and cell integrated capacity is also increased due to a plurality of float gate cell arrays deposited vertically using a plurality of cell oxide layers.

Abstract translation: 浮动栅极存储器件包括底部字线，形成在底部字线上并保持在浮置状态的浮动沟道层，浮动栅极和形成在浮动栅极上的与底部字线平行的顶部字线。 在浮动通道上形成的浮动门中，存储数据。 这里，根据底部字线和顶部字线的电平，将数据写入浮动栅极，并且根据存储在浮动栅极中的电荷的极性状态，将不同的通道电阻感应到浮动通道，从而读取数据 。 结果，在浮栅存储器件中，由于使用多个单元氧化物层垂直淀积的多个浮栅单元阵列，保持特性得到改善，并且单元集成能力也增加。

公开(公告)号：US20070103220A1

公开(公告)日：2007-05-10

申请号：US11479290

申请日：2006-06-29

Applicant: Dong-Hwan Kim ,  Si-Nae Kim ,  Kae-Dal Kwack ,  Jae-Jin Lee

Inventor： Dong-Hwan Kim ,  Si-Nae Kim ,  Kae-Dal Kwack ,  Jae-Jin Lee

IPC: G06F1/04

CPC classification number: G06F1/10

Abstract: A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.

Abstract translation: 提供时钟驱动程序。 第一驱动单元配置有多个驱动器并且接收第一时钟信号以驱动第一泵送时钟。 第二驱动单元配置有多个驱动器并且接收第二时钟信号以驱动第二抽时钟。 电荷循环开关连接在第一驱动单元的输出端和第二驱动单元的输出端之间。 开关控制器响应于第一和第二抽吸时钟信号选择性地将第一或第二驱动单元的输入时钟信号传送到电荷再循环开关。

公开(公告)号：US20070069778A1

公开(公告)日：2007-03-29

申请号：US11478094

申请日：2006-06-30

Applicant: Hoon Choi ,  Jae-Jin Lee

Inventor： Hoon Choi ,  Jae-Jin Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  G06F7/68 ,  H03L7/0805

Abstract: A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.

Abstract translation: 具有正常模式和掉电模式的存储器件的DLL包括用于缓冲外部时钟信号以输出内部时钟信号的时钟缓冲器。 断电模式控制器响应于时钟使能信号产生掉电模式控制信号以定义正常模式或掉电模式。 源时钟生成单元在停电模式控制信号的控制下接收内部时钟信号以产生DLL源时钟信号。 相位更新单元基于DLL源时钟信号执行相位更新操作，以输出DLL时钟信号。

公开(公告)号：US07195712B2

公开(公告)日：2007-03-27

申请号：US10505424

申请日：2002-06-05

Applicant: Jong Bok Park ,  Jae Jin Lee ,  Yong Dae Jeong ,  Gyung Hae Aoh

Inventor： Jong Bok Park ,  Jae Jin Lee ,  Yong Dae Jeong ,  Gyung Hae Aoh

IPC: C02F3/30

CPC classification number: C02F3/308 ,  Y10S210/903 ,  Y10S210/906

Abstract: Provided is a wastewater treatment apparatus for removing nitrogen and phosphorus having an anaerobic tank, an anoxic tank, an aerobic tank and a clarifier, wherein the aerobic tank includes has a baffle installed at one side thereof to form a dissolved oxygen reducing zone for reducing the concentration of dissolved oxygen contained in internally recycled wastewater returned from a dissolved oxygen reducing zone while increasing the concentration of dissolved oxygen contained in treated effluent supplied from a part other than the dissolved oxygen reducing zone of the aerobic tank to a clarifier in a subsequent stage. Since organic matter present in wastewater is effectively used, the efficiency of removing nitrogen and phosphorus can be increased and the amounts of oxygen required throughout the treatment process and organic matter required for denitrification can be reduced. Also, synthesis of cells of microorganisms is suppressed. Therefore, the repair and maintenance costs can be reduced.

Abstract translation: 提供了一种用于除去具有厌氧池，缺氧罐，好氧池和澄清池的氮和磷的废水处理装置，其中需氧罐包括在其一侧安装有挡板以形成溶解氧还原区，用于减少 从溶解氧还原区返回的内部再循环废水中所含的溶解氧的浓度，同时将从需氧罐的溶解氧还原区以外的部分供给的处理流出物中所含的溶解氧浓度提高到后续阶段的澄清池。 由于废水中存在的有机物质被有效地利用，所以可以提高氮和磷的除去效率，并且可以减少整个处理过程所需的氧气量和反硝化所需的有机物质。 此外，抑制微生物细胞的合成。 因此，可以降低维修和维护成本。

公开(公告)号：US20060238215A1

公开(公告)日：2006-10-26

申请号：US11322789

申请日：2005-12-29

Applicant: Kyung-Whan Kim ,  Jae-Jin Lee

Inventor： Kyung-Whan Kim ,  Jae-Jin Lee

IPC: H03K19/195 ,  G11C19/08

CPC classification number: G11C7/1075

Abstract: A multi-port memory device improves efficiency of a global data drive by controlling the global data bus to transmit data in a predetermined range. The multi-port memory device includes a global data bus; transmitters and receivers; a termination unit for controlling the global data bus to transmit the data in a range between a first voltage and a second voltage in response to an active mode signal; and a voltage generator for generating the first and the second voltages. The first voltage is higher than a ground voltage and the second voltage is lower than a power supply voltage.

Abstract translation: 多端口存储器件通过控制全局数据总线在预定范围内传输数据来提高全局数据驱动的效率。 多端口存储器件包括全局数据总线; 发射机和接收机; 终端单元，用于响应于活动模式信号，控制全局数据总线在第一电压和第二电压之间的范围内传输数据; 以及用于产生第一和第二电压的电压发生器。 第一电压高于接地电压，第二电压低于电源电压。