公开(公告)号：US1631916A

公开(公告)日：1927-06-07

申请号：US7176525

申请日：1925-11-27

Applicant: JAMES CHAMBERS

Inventor： JAMES CHAMBERS

IPC: B25B7/02 ,  B25B7/10 ,  B25B7/22

CPC classification number: B25B7/22 ,  B25B7/02 ,  B25B7/10

公开(公告)号：US08076099B2

公开(公告)日：2011-12-13

申请号：US12133963

申请日：2008-06-05

Applicant: James Chambers ,  Jieh-Juen Yu ,  Karl E. Klose ,  M. Neal Guentzel ,  Bernard P. Arulanandam

Inventor： James Chambers ,  Jieh-Juen Yu ,  Karl E. Klose ,  M. Neal Guentzel ,  Bernard P. Arulanandam

IPC: C12Q1/02 ,  C12Q1/37

CPC classification number: G01N33/56911 ,  A61K2039/543 ,  C12Q1/42

Abstract: The instant invention concerns Francisella bacteria mediated degradation of alkaline phosphatase (AP). Detection of AP degradation may be used to determine the presence of Francisella bacteria in a sample. Furthermore, methods for identifying and treating Francisella infections by detecting AP degradation are described. Methods of the invention also concerns methods for treating Francisella infection by inhibiting AP degradation.

Abstract translation: 本发明涉及弗朗西斯细菌介导的碱性磷酸酶（AP）的降解。 AP降解的检测可用于确定样品中弗朗西斯氏菌属细菌的存在。 此外，描述了通过检测AP降解来鉴定和治疗弗朗西斯病菌感染的方法。 本发明的方法还涉及通过抑制AP降解来治疗弗朗西斯氏菌感染的方法。

公开(公告)号：US20100000723A1

公开(公告)日：2010-01-07

申请号：US12280481

申请日：2007-02-16

Applicant: Colin James Chambers

Inventor： Colin James Chambers

IPC: F28D1/04 ,  C02F1/02

CPC classification number: F28D1/0213 ,  C02F1/001 ,  C02F1/02 ,  C02F1/76 ,  C02F2103/002 ,  C02F2209/40 ,  C02F2209/44 ,  C02F2303/04 ,  C12M23/36 ,  C12M41/18 ,  C12M41/20 ,  C12P5/023 ,  F28D1/06 ,  F28D7/106 ,  Y02E50/343

Abstract: A system, method and apparatus for transferring heat are disclosed. They make use of the first receptacle having an inlet for ingress of the first liquid, such as sewage, and an outlet for egress of the first liquid. Also provided is a second receptacle having an inlet for ingress of the second liquid, such as exhausted heated water from an air conditioning or cooling unit, and an outlet for egress of the second liquid. The second receptacle comprises a portion located in a proximity of the first receptacle. The first and second receptacles are arranged such that they allow a quantity of heat to transfer from the second liquid to the first liquid. The apparatus may be configured for inline connection to a sewerage main.

Abstract translation: 公开了一种用于传递热量的系统，方法和装置。 它们利用具有用于第一液体（例如污水）进入的入口的第一容器和用于排出第一液体的出口。 还提供了第二容器，其具有用于进入第二液体的入口，例如来自空调或冷却单元的排出的加热水，以及用于排出第二液体的出口。 第二容器包括位于第一容器附近的部分。 第一和第二容器被布置成使得它们允许一定量的热量从第二液体转移到第一液体。 该设备可以被配置成与污水处理主体进行内联连接。

公开(公告)号：US20070042555A1

公开(公告)日：2007-02-22

申请号：US11205477

申请日：2005-08-17

Applicant: Hiroaki Niimi ,  Luigi Colombo ,  James Chambers

Inventor： Hiroaki Niimi ,  Luigi Colombo ,  James Chambers

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/8234

CPC classification number: H01L21/823462 ,  H01L21/28185 ,  H01L21/28229 ,  H01L21/31645 ,  H01L21/823857 ,  H01L21/8249 ,  H01L29/517

Abstract: The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising the metal is formed over the metal source layer (210).

Abstract translation: 本发明提供了形成栅极电介质的方法，其包括在衬底（110）上形成包括金属和至少一种非金属元素的金属源层（210）。 金属源层（210）形成为具有富含金属的组成。 在金属源层（210）之上形成包括金属的电介质层（310）。

公开(公告)号：US20070037335A1

公开(公告)日：2007-02-15

申请号：US11204235

申请日：2005-08-15

Applicant: James Chambers ,  Luigi Colombo ,  Mark Visokay

Inventor： James Chambers ,  Luigi Colombo ,  Mark Visokay

IPC: H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L29/4966

Abstract: Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.

Abstract translation: 同时形成具有各自功函数的不同金属栅极晶体管。 在一个实例中，在半导体衬底上形成具有较低功函数的金属碳化物。 然后在第二区域中将氧和/或氮添加到金属碳化物中以在第二区域中建立第二功函数，其中金属碳化物本身在第一区域中建立第一功函数。 然后在第一区域中形成一个或多个第一金属栅极晶体管类型，并且在第二区域中形成一个或多个第二金属栅极晶体管类型。

公开(公告)号：US20060267119A1

公开(公告)日：2006-11-30

申请号：US11462573

申请日：2006-08-04

Applicant: Luigi Colombo ,  James Chambers ,  Mark Visokay

Inventor： Luigi Colombo ,  James Chambers ,  Mark Visokay

IPC: H01L29/94

CPC classification number: H01L21/823842 ,  H01L29/4958

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract translation: 本发明在一个实施例中提供一种栅极结构（100）。 栅极结构包括栅极电介质（105）和栅极（110）。 栅极电介质包括难熔金属并且位于半导体衬底（115）之上。 半导体衬底具有导带和价带。 栅极位于栅极电介质上方并且包括难熔金属。 栅极具有与导带或价带对准的功函数。 其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。

公开(公告)号：US20060258074A1

公开(公告)日：2006-11-16

申请号：US11127737

申请日：2005-05-12

Applicant: Mark Visokay ,  James Chambers ,  Luigi Colombo

Inventor： Mark Visokay ,  James Chambers ,  Luigi Colombo

IPC: H01L21/8238 ,  H01L21/4763

CPC classification number: H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that form metal silicide gates and mitigate formation of silicide region defects near channel regions. A dielectric layer is formed over a semiconductor device (306). Polysilicon is deposited on the dielectric layer to form a gate electrode layer (308) and a patterning operation is then performed to form gate structures (310). Source/drain regions are formed (320) and the gate structures are tuned to obtain a selected work function (324). A metal is then selectively deposited on only the gate structures (328) and a thermal process is performed that reacts the deposited metal with polysilicon of the gate layer to obtain a metal suicide material (330).

Abstract translation: 本发明通过提供形成金属硅化物栅极的制造方法和减少沟道区附近的硅化物区域缺陷的形成来促进半导体制造。 在半导体器件（306）上形成电介质层。 多晶硅沉积在电介质层上以形成栅极电极层（308），然后执行构图操作以形成栅极结构（310）。 源极/漏极区域形成（320）并且栅极结构被调谐以获得所选择的功函数（324）。 然后仅在栅极结构（328）上选择性地沉积金属，并且执行使沉积的金属与栅极层的多晶硅反应以获得金属硅化物材料（330）的热处理。

公开(公告)号：US20060246651A1

公开(公告)日：2006-11-02

申请号：US11118843

申请日：2005-04-29

Applicant: James Chambers ,  Mark Visokay ,  Luigi Colombo

Inventor： James Chambers ,  Mark Visokay ,  Luigi Colombo

IPC: H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

Abstract translation: 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

公开(公告)号：US20050184319A1

公开(公告)日：2005-08-25

申请号：US11112463

申请日：2005-04-21

Applicant: James Chambers ,  Mark Visokay

Inventor： James Chambers ,  Mark Visokay

IPC: H01L21/00 ,  H01L21/336 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66795

Abstract: Transistors and fabrication methods are presented in which a semiconductor body is deposited in a cavity of a temporary form structure above a semiconductor starting structure. The formed semiconductor body can be epitaxial silicon deposited in the form cavity over a silicon substrate, and includes three body portions, two of which are doped to form source/drains, and the other forming a transistor channel that overlies the starting structure. A gate structure is formed along one or more sides of the channel body portion to create a MOS transistor.

Abstract translation: 提出了晶体管和制造方法，其中半导体体沉积在半导体起始结构之上的临时形式结构的空腔中。 所形成的半导体本体可以是外延硅沉积在硅衬底上的空腔中，并且包括三个主体部分，其中两个被掺杂以形成源极/漏极，另一个形成覆盖起始结构的晶体管沟道。 栅极结构沿通道主体部分的一侧或多侧形成以形成MOS晶体管。

公开(公告)号：US20050136690A1

公开(公告)日：2005-06-23

申请号：US10739617

申请日：2003-12-18

Applicant: Luigi Colombo ,  James Chambers ,  Mark Visokay ,  Antonio Rotondaro

Inventor： Luigi Colombo ,  James Chambers ,  Mark Visokay ,  Antonio Rotondaro

IPC: C23C16/56 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L21/31 ,  H01L21/8242 ,  H01L21/469

CPC classification number: H01L21/02318 ,  C23C16/56 ,  H01L21/02323 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/318 ,  H01L29/518 ,  H01L29/78

Abstract: A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.

Abstract translation: 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。