摘要:
The image sensor charge detection amplifier has a charge storage well 60, a charge sensor 32 for sensing charge levels in the charge storage well 60, a charge drain 28 adjacent to the charge storage well 60, and charge transfer structures for transferring charge from the charge storage well 60 to the charge drain 28.
摘要:
The charge coupled device charge detection node includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type in the substrate; virtual gate regions of the first conductivity type formed in the second semiconductor layer, the virtual gate regions forming virtual phase potential areas; an insulating layer on the second semiconductor layer; a floating gate formed on the insulating layer, the floating gate is located above a portion of the second semiconductor layer that is between virtual gate regions, the floating gate forming a floating gate potential well in response to a voltage; a first transfer gate formed on the insulating layer and separated from the floating gate by a virtual gate region, the first transfer gate forming a transfer potential area in response to a voltage; and an electrode coupled to one of the virtual gate regions on the opposite side of the floating gate from the first transfer gate, the electrode increases the potential of the virtual phase potential area below the electrode in response to a voltage.
摘要:
The image sensor charge detection amplifier has a charge storage well 60, a charge sensor 32 for sensing charge levels in the charge storage well 60, a charge drain 28 adjacent to the charge storage well 60, and charge transfer structures for transferring charge from the charge storage well 60 to the charge drain 28.
摘要:
Described is a new high performance CCD image sensor technology which can be used to build a versatile image senor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.
摘要翻译:描述了一种新的高性能CCD图像传感器技术,可用于构建具有高分辨率和高像素密度的传感器的通用图像传感器系列。 所描述的传感器架构基于新的充电超扫描概念,其被开发用于克服诸如开花和图像涂片的常见问题。 电荷超扫描发生在位于类似于Interline Transfer CCD器件的光电子之间的非常窄的垂直通道中。 这里的区别在于,在任何相当长的时间内,电荷从不存储在这些区域中,并且使用新的电阻栅极行波扫描技术扫除。 电荷超扫描方法还允许在单个水平消隐间隔期间将位于阵列中任何位置的光子的几行数据快速电荷传输到缓冲存储器中。
摘要:
The dynamic range of an image array photosite is improved by, first, turning on a column clamp transistor having a source coupled to a photosite transistor source and a drain coupled to a photosite transistor drain, wherein the column clamp transistor is turned on by a column clamp transistor gate voltage; then decreasing a current supplied to a column sense line below a quiescent value, wherein the column sense line is coupled to the photosite transistor source; then turning on the photosite transistor by a photosite transistor gate voltage; then turning off the photosite transistor and the column clamp transistor at substantially the same time; then increasing the current above the quiescent value; and then returning the current to the quiescent value.
摘要:
A virtual phase, buried channel CCD with the usual metal gate/oxide structure replaced by a reverse biased junction (possibly a heterojunction) or Schottky barrier is disclosed. Such gate substitution for a standard three phase or multiphase CCD and other devices compatibly fabricated with such gate are also disclosed.
摘要:
Disclosed is a method for etching a tin oxide layer (18). The tin oxide layer (18) is masked by selectively forming an etchant-resistant material (20) on it. This material is itself patterned and etched, and then the exposed tin oxide (26) is isotropically etched such that substantially all of the exposed tin oxide (26) is removed. The preferred etchant of the invention comprises a major portion of inert nitrogen gas with a minor portion of hydrogen iodide. A vertical wall reactor (48) is provided for use with the invention in order to achieve a uniform flow and etch rate. In an alternate embodiment, a plasma reactor can be used to perform the etching.
摘要:
A CCD imager of small geometry which has increased well capacity. An additional p-type implant 112 selectively located creates a p-type region 112 below the channel region 13 of the virtual well regions 34, which increases the capacitance in the virtual well regions 34.
摘要:
A CCD imager with a correlated clamp sample and hold amplifier on chip includes a chain of CCD wells, a charge-sensing node coupled to one end of the chain of CCD wells, and a clock to clock charge packets from the chain of CCD wells into the charge-sensing node. A dummy charge-sensing node is integrated into the same monocrystalline semiconductor substrate as the charge-sensing node, and the charge-sensing node and the dummy node are connected to a common reference voltage. An amplifier senses a predetermined voltage change on the charge-sensing node with reference to the voltage on the dummy node after a charge packet has been transferred into the charge-sensing node.
摘要:
A color CCD imager with three correlated clamp-sample-and-hold sense amplifiers (one for each color channel). The three control lines necessary to operate this type of amplifier, together with the clock lines necessary for the three shift registers which feed them, are all wired together, so that correct phasing of the three outputs is maintained with only three clock lines.