公开(公告)号：US20050085039A1

公开(公告)日：2005-04-21

申请号：US10901347

申请日：2004-07-29

Applicant: Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

Inventor： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4232 ,  H01L29/792

Abstract: In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.

Abstract translation: 在其中使用电荷存储膜的非易失性存储器的MOS晶体管和用于选择它的MOS晶体管相邻形成的分离栅极型非易失性存储单元中，电荷存储特性得到改善，栅电极的电阻降低。 为了防止电荷存储薄膜的拐角部分的厚度减小并且提高电荷存储特性，在选择栅电极的侧壁上形成锥形。 此外，为了稳定地进行用于降低自对准栅电极的电阻的硅化物工艺，选择栅电极的侧壁凹陷。 或者，在自对准栅电极的上部和选择栅电极的上部之间形成不连续。

公开(公告)号：US06589871B2

公开(公告)日：2003-07-08

申请号：US09941757

申请日：2001-08-30

Applicant: Yoshio Kawamura ,  Souichi Katagiri ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

Inventor： Yoshio Kawamura ,  Souichi Katagiri ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

IPC: H01L21302

CPC classification number: H01L22/20

Abstract: A processing method capable of presenting the processing condition with a high accuracy to improve the productivity, including a step of applying a first processing to a first substrate and a step of applying a second processing to the first substrate or the second processing to a second substrate and determining a correlation function for each of in-plane positions as the data for the difference in a plurality of processing steps to each of the in-plane positions in view of on the in-plain distribution data to the in-plane position of each of the substrate as a result of the plurality of processings, calculating the in-plain distribution characteristics of the substrate under a desired processing condition in view of the correlation function and processing the substrate based on the in-plain distribution characteristics.

Abstract translation: 一种处理方法，其能够高精度地呈现处理条件以提高生产率，包括对第一基板施加第一处理的步骤和对第一基板施加第二处理的步骤或第二处理的步骤 以及将每个平面内位置的相关函数确定为多个处理步骤中的差数据的数据，以便在每个平面内位置中考虑到不均匀分布数据到每个平面内位置的平面内位置 作为多个处理的结果，考虑到相关函数，在所需的处理条件下计算衬底的不均匀分布特性，并且基于平原分布特性来处理衬底。

公开(公告)号：US06524961B1

公开(公告)日：2003-02-25

申请号：US09359760

申请日：1999-07-22

Applicant: Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

Inventor： Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

IPC: H01L21461

CPC classification number: B24B37/245 ,  B24D3/32 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

公开(公告)号：US06477825B2

公开(公告)日：2002-11-12

申请号：US10124457

申请日：2002-04-18

Applicant: Souichi Katagiri ,  Kan Yasui

Inventor： Souichi Katagiri ,  Kan Yasui

IPC: B24B100

CPC classification number: B24B53/017

Abstract: With a time control means for a wetting treatment of a fixed abrasive platen provided, the fixed abrasive platen is set in a good wet state in advance prior to the start of polishing. The time control means may be incorporated in the body of a flattening/machining apparatus, or alternatively a wetting retaining mean may newly be separately provided instead. While the fixed abrasive platen is rapidly transformed through expansion due to wetting, the wetting treatment is desirably performed till a transformation ratio thereof is stabilized at 0.0005% or less.

公开(公告)号：US08810946B2

公开(公告)日：2014-08-19

申请号：US13641239

申请日：2011-03-28

Applicant: Kan Yasui ,  Harukazu Miyamoto ,  Masukazu Igarashi

Inventor： Kan Yasui ,  Harukazu Miyamoto ,  Masukazu Igarashi

IPC: G11B5/127

CPC classification number: G11B5/3146 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/314 ,  G11B5/315 ,  G11B2005/0024

Abstract: A microwave-assisted magnetic recording system configured to perform magnetic recording with high density, including a high-frequency magnetic field generation element whose width is narrower than a track width of a main pole. A magnetic field vector from the main pole is perpendicularly incident on a film surface of the high-frequency magnetic field generating unit, by a shield material arranged to have a high magnetic permeability so that the main pole magnetic field is corrected and induced, and a hard bias layer to which a desired static magnetic field is added. Areas having high magnetic field gradients overlap each other by performing an offset of the high-frequency magnetic field generating unit of the magnetic head from the central line of the main pole.

Abstract translation: 一种被配置为执行高密度磁记录的微波辅助磁记录系统，包括宽度窄于主极的轨道宽度的高频磁场产生元件。 来自主极的磁场矢量垂直入射在高频磁场产生单元的膜表面上，通过屏蔽材料被布置成具有高导磁率，使得主极磁场被校正和感应，并且 添加了期望的静磁场的硬偏压层。 通过从主极的中心线执行磁头的高频磁场产生单元的偏移，具有高磁场梯度的区域彼此重叠。

公开(公告)号：US20130140622A1

公开(公告)日：2013-06-06

申请号：US13755348

申请日：2013-01-31

Applicant: Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

公开(公告)号：US08390053B2

公开(公告)日：2013-03-05

申请号：US12188412

申请日：2008-08-08

Applicant: Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L29/792

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract translation: 插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为 小于40nm。 因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。 此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

公开(公告)号：US08193053B2

公开(公告)日：2012-06-05

申请号：US12763402

申请日：2010-04-20

Applicant: Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

Inventor： Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/792

Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times.In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

Abstract translation: 本发明的目的是提供一种可以高速读取并重新编程次数增加的集成半导体非易失性存储装置。 在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。 为了克服这个问题，本发明的集成半导体非易失性存储装置被配置为使得具有不同存储器栅极长度的存储单元集成在同一芯片上。 这允许以高速读取设备并重新编程增加的次数。

公开(公告)号：US20100302688A1

公开(公告)日：2010-12-02

申请号：US12784405

申请日：2010-05-20

Applicant: Masato Shiimoto ,  Kan Yasui ,  Nobuo Yoshida ,  Hiroyuki Takazawa

Inventor： Masato Shiimoto ,  Kan Yasui ,  Nobuo Yoshida ,  Hiroyuki Takazawa

IPC: G11B5/127

CPC classification number: G11B5/3932 ,  B82Y25/00 ,  G01R33/093 ,  G01R33/098 ,  H01L43/08 ,  H01L43/10

Abstract: According to one embodiment, a magnetoresistive effect head includes a lower magnetic shield provided on a substrate, a magnetoresistive effect film laminated from a pinned layer with a pinned direction of magnetization, an intermediate layer, a free layer having a varying direction of magnetization controlled by an applied external magnetic field, a magnetic domain control layer formed with an intervening insulation layer on both sides in a track width direction of the magnetoresistive effect film, an upper magnetic shield, and electrodes for directing sense current flow in a direction perpendicular to a film surface of the magnetoresistive effect film, wherein a magnetic field applied by the magnetic domain control layer to a region away from an ABS of the free layer is at least 1.4 times larger than a magnetic field applied by the magnetic domain control layer to a region near the ABS of the free layer.

Abstract translation: 根据一个实施例，磁阻效应头包括设置在基板上的下磁屏蔽，从具有钉扎方向的钉扎层层压的磁阻效应膜，中间层，具有变化的磁化方向的自由层， 施加的外部磁场，在磁阻效应膜的磁道宽度方向上在两侧形成有中间绝缘层的磁畴控制层，上磁屏蔽和用于引导垂直于膜的方向的感测电流的电极 磁阻效应膜的表面，其中由磁畴控制层施加到远离自由层的ABS的区域的磁场比由磁畴控制层施加到接近的区域的磁场的至少大1.4倍 ABS的自由层。

公开(公告)号：US20100232231A1

公开(公告)日：2010-09-16

申请号：US12787158

申请日：2010-05-25

Applicant: Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C16/06 ,  G11C11/34

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。