公开(公告)号：US20080215822A1

公开(公告)日：2008-09-04

申请号：US11933178

申请日：2007-10-31

Applicant: Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20050144339A1

公开(公告)日：2005-06-30

申请号：US10746481

申请日：2003-12-24

Applicant: Mahesh Wagh ,  Buck Gremel ,  Naveen Bohra

Inventor： Mahesh Wagh ,  Buck Gremel ,  Naveen Bohra

IPC: G06F3/00 ,  H04L29/06 ,  H04L29/08

CPC classification number: H04L69/12 ,  H04L69/32

Abstract: A receiving device in which transaction layer packets are speculatively forwarded, is disclosed. The receiving device includes a physical layer, a link layer, a transaction layer, and a core. Transaction layer packets are forwarded to the transaction layer before processing at the link layer is completed, and without the use of memory storage at the link layer. A link layer engine checks the sequence number only and not the CRC before forwarding the packet to the transaction layer. This allows the transaction layer to pre-process the packet, such as verifying header information. However, the transaction layer is unable to make the transaction globally available until the link layer has verified the CRC of the packet. The simultaneous processing of the packet by both the link layer and the transaction layer may reduce latency and lessens the amount of memory needed for processing.

Abstract translation: 披露了事务层分组被推测转发的接收设备。 接收设备包括物理层，链路层，事务层和核心。 在链路层处理完成之前，事务层数据包被转发到事务层，而不用在链路层使用存储器。 链路层引擎仅在将数据包转发到事务层之前检查序列号而不是CRC。 这允许事务层预处理数据包，例如验证头信息。 然而，事务层无法使事务全局可用，直到链路层已经验证了数据包的CRC。 通过链路层和事务层同时处理数据包可以减少延迟并减少处理所需的存储量。

公开(公告)号：US20210232520A1

公开(公告)日：2021-07-29

申请号：US17231152

申请日：2021-04-15

Applicant: Swadesh Choudhary ,  Mahesh Wagh ,  Debendra Das Sharma

Inventor： Swadesh Choudhary ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/38 ,  G06F13/40 ,  G06F11/10

Abstract: In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

公开(公告)号：US09563260B2

公开(公告)日：2017-02-07

申请号：US13840172

申请日：2013-03-15

Applicant: Mahesh Wagh ,  Su Wei Lim

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G08C17/00 ,  G06F1/32 ,  H04W52/02 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F9/4418 ,  G06F13/4295 ,  H04W52/0203 ,  Y02D10/151 ,  Y02D10/157 ,  Y02D70/1222 ,  Y02D70/1226 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/166

Abstract: Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.

Abstract translation: 描述用于将端口条目同步到最低功率状态的系统，装置和方法。 在进入最低功率状态之前，端口的所有逻辑被置于中间状态。

公开(公告)号：US08972640B2

公开(公告)日：2015-03-03

申请号：US13534541

申请日：2012-06-27

Applicant: Mahesh Wagh

Inventor： Mahesh Wagh

IPC: G06F13/42 ,  G06F13/36

CPC classification number: G06F13/4027 ,  G06F13/385 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括访问第一设备的第一链路能力寄存器的第一字段，其具有根据第一通信协议的协议栈和具有物理层的协议栈的物理层的包括事务层和链路层的协议栈 第二通信协议的单元，使用第一字段作为第一设备的第二链路能力寄存器中的位置的指针值，以及使用来自第二链路能力寄存器中的位置的信息来执行物理链路的配置操作 耦合到设备。 描述和要求保护其他实施例。

公开(公告)号：US20140281753A1

公开(公告)日：2014-09-18

申请号：US13840394

申请日：2013-03-15

Applicant: Mahesh Wagh ,  Su Wei Lim

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G06F11/07 ,  G06F1/32

CPC classification number: G06F11/0757 ,  G06F1/3293 ,  G06F11/0745 ,  G06F13/4295 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, apparatuses, and method for handling timeouts in a link state training sequence are described. All modules of a port undergoing link state training placed into an intermediate state prior to entry into the lowest power state.

Abstract translation: 描述了用于处理链路状态训练序列中的超时的系统，装置和方法。 正在进行链路状态训练的端口的所有模块在进入最低功率状态之前置于中间状态。

公开(公告)号：US08819388B2

公开(公告)日：2014-08-26

申请号：US13550966

申请日：2012-07-17

Applicant: Zhen Fang ,  Mahesh Wagh ,  Jasmin Ajanovic ,  Michael E. Espig ,  Ravishankar Iyer

Inventor： Zhen Fang ,  Mahesh Wagh ,  Jasmin Ajanovic ,  Michael E. Espig ,  Ravishankar Iyer

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0292 ,  G06F12/0888 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/206

Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.

Abstract translation: 描述了用于控制片上系统结构（OSF）块的方法和装置。 在一个实施例中，响应于用户级请求可以存储对应于物理地址的影子地址，并且逻辑电路（例如，存在于OSF中）可以从影子地址确定物理地址。 还公开了其他实施例。

公开(公告)号：US20140237155A1

公开(公告)日：2014-08-21

申请号：US14262158

申请日：2014-04-25

Applicant: Ken Shoemaker ,  Mahesh Wagh ,  Woojong Han ,  Madhu Athreya ,  Arvind Mandhani ,  Shreekant S. Thakkar

Inventor： Ken Shoemaker ,  Mahesh Wagh ,  Woojong Han ,  Madhu Athreya ,  Arvind Mandhani ,  Shreekant S. Thakkar

IPC: G06F13/40

CPC classification number: G06F13/404 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4045

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一接口依次通过一个或多个物理单元耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将实现用于IP核的PC协议的报头以使能 无需修改即可并入设备。 描述和要求保护其他实施例。

公开(公告)号：US20140108697A1

公开(公告)日：2014-04-17

申请号：US14132610

申请日：2013-12-18

Applicant: Mahesh Wagh

Inventor： Mahesh Wagh

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/385 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括访问第一设备的第一链路能力寄存器的第一字段，其具有根据第一通信协议的协议栈和具有物理层的协议栈的物理层的包括事务层和链路层的协议栈 第二通信协议的单元，使用第一字段作为第一设备的第二链路能力寄存器中的位置的指针值，以及使用来自第二链路能力寄存器中的位置的信息来执行物理链路的配置操作 耦合到设备。 描述和要求保护其他实施例。

公开(公告)号：US20140068135A1

公开(公告)日：2014-03-06

申请号：US14011009

申请日：2013-08-27

Applicant: David J. Harriman ,  Mahesh Wagh ,  Robert E. Gough ,  James E. Jaussi

Inventor： David J. Harriman ,  Mahesh Wagh ,  Robert E. Gough ,  James E. Jaussi

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F1/3203 ,  G06F13/20 ,  G06F13/4295 ,  G06N99/005 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有事务层和链路层的协议栈。 另外，第一物理（PHY）单元被耦合到协议栈，以经由物理链路提供处理器和耦合到处理器的设备之间的通信，其中第一PHY单元是低功率通信协议，并且包括第一物理 单位电路。 反过来，第二PHY单元被耦合到协议栈，以经由耦合在与物理链路分离的多核处理器和设备之间的边带信道来提供处理器和设备之间的通信，其中第二PHY单元包括第二物理单元 电路。 描述和要求保护其他实施例。