公开(公告)号：US11677011B2

公开(公告)日：2023-06-13

申请号：US17126584

申请日：2020-12-18

Applicant: OmniVision Technologies, Inc.

Inventor： Yuanliang Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L27/146 ,  H01L21/308 ,  H01L29/423

CPC classification number: H01L29/66613 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/308 ,  H01L21/31144 ,  H01L27/14614 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/4236

Abstract: A method of fabricating transistors with a vertical gate in trenches includes lithographing to form wide trenches; forming dielectric in the trenches and filling the trenches with flowable material; and lithography to form narrow trenches within the wide trenches thereby exposing well or substrate before epitaxially growing semiconductor strips atop substrate exposed by the narrow trenches; removing the flowable material; growing gate oxide on the semiconductor strip; forming gate conductor over the gate oxide and into gaps between the epitaxially-grown semiconductor strips and the dielectric; masking and etching the gate conductor; and implanting source and drain regions. The transistors formed have semiconductor strips extending from a source region to a drain region, the semiconductor strips within trenches, the trench walls insulated with a dielectric, a gate oxide formed on both vertical walls of the semiconductor strip; and gate material between the dielectric and gate oxide.

公开(公告)号：US11670662B2

公开(公告)日：2023-06-06

申请号：US17133553

申请日：2020-12-23

Applicant: OmniVision Technologies, Inc.

Inventor： Cynthia Sun Yee Lee ,  Shiyu Sun

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/1462 ,  H01L27/14645 ,  H01L27/14685

Abstract: An image sensor with passivated full deep-trench isolation includes a semiconductor substrate, the substrate including a plurality of sidewalls that form a plurality of trenches that separates pixels of a pixel array, and a passivation layer lining the plurality of sidewall surfaces and the back surface of the semiconductor substrate. A method for forming an image sensor with passivated full deep-trench isolation includes forming trenches in a semiconductor substrate, filling the trenches with a sacrificial material, forming a plurality of photodiode regions, forming a circuit layer, thinning the semiconductor substrate, and removing the sacrificial material. A method for reducing noise in an image sensor includes removing material from a semiconductor substrate to form a plurality of trenches that extend from a front surface toward a back surface, and depositing a dielectric material onto the back surface and into the plurality of trenches through a back opening of each trench.

公开(公告)号：US11644606B1

公开(公告)日：2023-05-09

申请号：US17501586

申请日：2021-10-14

Applicant: OmniVision Technologies, Inc.

Inventor： Victor Lenchenkov

IPC: G02B5/30 ,  H04N5/232

CPC classification number: G02B5/3058 ,  H04N5/23229

Abstract: An image sensor configured to resolve intensity and polarization has multiple pixels each having a single microlens adapted to focus light on a central photodiode surrounded by at least a first, a second, a third, and a fourth peripheral photodiodes, where a first polarizer at a first angle is disposed upon the first peripheral photodiode, a third polarizer at a third angle is disposed upon the third peripheral photodiode, a second polarizer at a second angle is disposed upon the second peripheral photodiode, and a fourth polarizer at a fourth angle is disposed upon the fourth peripheral photodiode, the first, second, third, and fourth angles being different. In embodiments, 4 or 8 peripheral photodiodes are provided, and in an embodiment the polarizers are parts of an octagonal polarizer.

公开(公告)号：US11632512B2

公开(公告)日：2023-04-18

申请号：US17180520

申请日：2021-02-19

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Min Qu ,  Chao-Fang Tsai ,  Chun-Hsiang Chang

IPC: H04N5/378 ,  H03M1/12 ,  G06F7/575 ,  G06F7/507 ,  H03M1/28

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

公开(公告)号：US11627273B2

公开(公告)日：2023-04-11

申请号：US17217950

申请日：2021-03-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tao Sun

IPC: H03M1/56 ,  H04N5/378 ,  H03K4/06 ,  H03K3/037 ,  H03M1/12 ,  H03K4/90 ,  H03M1/34 ,  H03K19/20

Abstract: A ramp generator includes a plurality of switched current sources coupled in parallel between a resistor and ground. A digital ramp control signal generator includes a counter to generate a ramp control signal in response to a clock signal. Each bit of the ramp control signal is coupled to control switching of a respective one of the plurality of switched current sources to generate a ramp signal at an output of the ramp generator. The digital ramp control signal generator is coupled to receive a reset signal to zero the ramp control signal. The digital ramp control signal generator is further coupled to receive a set bits signal to initialize the ramp signal to a preset value after every reset of the ramp control signal to add a DC offset compensation current determined by the preset value to the ramp signal.

公开(公告)号：US11616088B2

公开(公告)日：2023-03-28

申请号：US16830086

申请日：2020-03-25

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sing-Chung Hu ,  Seong Yeol Mun ,  Bill Phan

IPC: H01L27/146 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78

Abstract: Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. The transistor includes a nonplanar structure disposed in the semiconductor substrate, which is bounded by two outer trench structures formed in the semiconductor substrate. Isolation deposits are disposed within the two outer trench structures formed in the semiconductor substrate. A gate includes a planar gate and two fingers extending into one of two inner trench structures formed in the semiconductor substrate between the nonplanar structure and a respective one of the two outer trench structures. This structure creates an electron channel extending along a plurality of sidewall portions of the nonplanar structure in a channel width plane.

公开(公告)号：US20230076598A1

公开(公告)日：2023-03-09

申请号：US18049668

申请日：2022-10-26

Applicant: OmniVision Technologies, Inc.

Inventor： Wei-Feng Lin ,  En-Chi Li ,  Chi-Chih Huang

IPC: H01L27/146

Abstract: An image sensor module comprises an image sensor having a light sensing area, a cover glass for covering the light sensing area, a dam between the image sensor and the cover glass, which surrounds the light sensing area, and has an outer wall and an inner wall, where a cross-section of the inner wall parallel to the surface of the light sensing area of the image sensor forms a sawtooth pattern and/or, where a cross-section of the inner wall orthogonal to the surface of the light sensing area of the image sensor forms an inclined surface.

公开(公告)号：US20230072103A1

公开(公告)日：2023-03-09

申请号：US17469461

申请日：2021-09-08

Applicant: OmniVision Technologies, Inc.

Inventor： Paul Wickboldt ,  Jau-Jan Deng ,  Shih-Hsin HSU

IPC: G06K9/00 ,  G06F3/042 ,  G06F3/041

Abstract: An optical fingerprint sensor with spoof detection includes a plurality of lenses, an image sensor including a pixel array that includes a plurality of first photodiodes and a plurality of second photodiodes, and at least one apertured baffle-layer having a plurality of aperture stops, wherein each second photodiode is configured to detect light having passed through a lens and at least one aperture stop not aligned with the lens along an optical axis. A method for detecting spoof fingerprints detected using an optical fingerprint sensor includes detecting large-angle light incident on a plurality of anti-spoof photodiodes, wherein the plurality of anti-spoof photodiodes is interleaved with a plurality of imaging photodiodes, determining an angular distribution of light based at least in part one the large-angle light, and detecting spoof fingerprints based at least in part on the angular distribution of light.

公开(公告)号：US20230067975A1

公开(公告)日：2023-03-02

申请号：US17463222

申请日：2021-08-31

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Seong Yeol Mun

IPC: H01L27/146

Abstract: An image sensor comprises a first photodiode, a second photodiode, and a deep trench isolation structure. The first photodiode and the second photodiode are each disposed within a semiconductor substrate. The first photodiode is adjacent to the second photodiode. The deep trench isolation structure has a varying depth disposed within the semiconductor substrate between the first photodiode and the second photodiode. The DTI structure extends the varying depth from a first side of the semiconductor substrate towards a second side of the semiconductor substrate. The first side of the semiconductor substrate is opposite of the second side of the semiconductor substrate.

公开(公告)号：US11574947B2

公开(公告)日：2023-02-07

申请号：US16996804

申请日：2020-08-18

Applicant: OmniVision Technologies, Inc.

Inventor： Hui Zang ,  Gang Chen

IPC: H01L27/146

Abstract: A photodiode array has buried photodiodes and vertical selection transistors. Trenches are lined with gate oxide and metallic plugs of first material lie within the trenches. Gate contacts of second material contact the metallic plugs, with photodiode diffusion regions adjacent the trenches as sources of vertical transistors, the metallic plugs form gates of the vertical transistors, and buried photodiode regions form sources of the vertical transistors. In embodiments, the first conductive material is tungsten, titanium nitride, titanium carbide, or aluminum and the second conductive material is polysilicon. The array is formed by trenching, growing gate oxide, and depositing first material in the trenches. The first material is etched to define metallic plugs, the second material is deposited onto the metallic plugs then masked and etched; and drain regions implanted. Etching the second material is performed by a reactive ion etch that stops upon reaching the metallic plugs.