公开(公告)号：US10379619B2

公开(公告)日：2019-08-13

申请号：US14553216

申请日：2014-11-25

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Marc Drader ,  Jérémie Teyssier ,  Olivier Pothier

IPC: G06F3/042 ,  G06F3/01 ,  G01C9/06 ,  G01B11/14 ,  G06F3/03 ,  G01S17/08 ,  G01S17/87

Abstract: A method for controlling an apparatus, includes steps of: determining distance measurements of an object in a first direction, using distance sensors defining between them a second direction different from the first direction, assessing a first inclination of the object in relation to a second direction based on the distance measurements, and determining a first command of the apparatus according to the inclination assessment.

公开(公告)号：US20190245258A1

公开(公告)日：2019-08-08

申请号：US16317082

申请日：2016-07-12

Applicant: STMicroelectronics SA

Inventor： Vincent KNOPIK ,  Boris MORET ,  Eric KERHERVE

IPC: H01P5/18

CPC classification number: H01P5/187 ,  H01P5/186

Abstract: A 90° hybrid inductive-capacitive coupling stage includes two first stage terminals capable of forming two stage inputs or two stage outputs and two second stage terminals capable of respectively forming two stage outputs or two stage inputs. The coupling stage is advantageously modular having a first stage axis of symmetry and a second stage axis of symmetry orthogonal to each other with neighboring inductive metal tracks being overlaid in at least one crossing region to form both an inductive circuit and a capacitive circuit. The metal tracks are coupled to the first stage terminals and to the second stage terminals such that the two first stage terminals are situated on one side of the first stage axis of symmetry and the two second stage terminals are situated on the other side of the first stage axis of symmetry.

公开(公告)号：US20190243165A1

公开(公告)日：2019-08-08

申请号：US16356915

申请日：2019-03-18

Applicant: STMicroelectronics SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/01 ,  G02F1/225 ,  H04B10/50 ,  G02F1/21 ,  G01J9/02 ,  G02F1/025 ,  G01J9/00

CPC classification number: G02F1/0123 ,  G01J9/00 ,  G01J9/02 ,  G02F1/025 ,  G02F1/218 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2201/58 ,  G02F2203/50 ,  H04B10/5053 ,  H04B10/50575

Abstract: An optical modulator uses an optoelectronic phase comparator configured to provide, in the form of an electrical signal, a measure of a phase difference between two optical waves. The phase comparator includes an optical directional coupler having two coupled channels respectively defining two optical inputs for receiving the two optical waves to be compared. Two photodiodes are configured to respectively receive the optical output powers of the two channels of the directional coupler. An electrical circuit is configured to supply, as a measure of the optical phase shift, an electrical signal proportional to the difference between the electrical signals produced by the two photodiodes.

公开(公告)号：US10367068B2

公开(公告)日：2019-07-30

申请号：US15427656

申请日：2017-02-08

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/36 ,  H01L29/786

Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

公开(公告)号：US20190230611A1

公开(公告)日：2019-07-25

申请号：US16250443

申请日：2019-01-17

Applicant: STMicroelectronics SA

Inventor： Marc Houdebine

IPC: H04W56/00 ,  H04L7/033

Abstract: Data frames, including bursts of an active load modulation (ALM) carrier signal generated from a modulation of an underlying carrier, are transmitted from an object to a reader. Synchronizing a reader carrier signal and the ALM carrier signal includes: prior to transmission of each data frame and between some of the bursts of the ALM carrier signal of each data frame, performing a closed-loop control of an output signal of a main oscillator onto a phase and a frequency of the reader carrier signal; estimating a ratio between a frequency of the output signal of the main oscillator and a frequency of a reference signal produced by a reference oscillator; and during each burst of the ALM carrier signal of each data frame, performing a closed-loop control in frequency only of the output signal of the main oscillator onto the reference frequency of the reference signal corrected by the ratio.

公开(公告)号：US10355649B2

公开(公告)日：2019-07-16

申请号：US15683236

申请日：2017-08-22

Applicant: STMicroelectronics SA

Inventor： Jean-Pierre Blanc ,  Severin Trochut

IPC: H03F3/04 ,  H03F1/30 ,  H03F1/02 ,  G05F3/30

Abstract: A voltage or current generator has a configurable temperature coefficient and includes a first voltage generator that generates a first voltage having a first negative temperature coefficient. A second voltage generator generates a second voltage having a second negative temperature coefficient different to the first negative temperature coefficient. A circuit generates an output level based on the difference between the first voltage scaled by a first scale factor and the second voltage scaled by a second scale factor.

公开(公告)号：US10340265B2

公开(公告)日：2019-07-02

申请号：US15694403

申请日：2017-09-01

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat

IPC: H02H9/04 ,  H01L27/02 ,  H01L27/06 ,  H01L49/02

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.

公开(公告)号：US10334168B2

公开(公告)日：2019-06-25

申请号：US16236043

申请日：2018-12-28

Applicant: STMicroelectronics SA

Inventor： Manu Alibay ,  Stéphane Auberger

IPC: H04N5/232 ,  G06T7/35 ,  H04N5/14 ,  G06T7/33

Abstract: A method determines a movement of an apparatus between capturing first and second images. The method includes testing model hypotheses of the movement by for example a RANSAC algorithm, operating on a set of first points in the first image and assumed corresponding second points in the second image to deliver the best model hypothesis. The testing includes, for each first point, calculating a corresponding estimated point using the tested model hypothesis, determining the back-projection error between the estimated point and the second point in the second image, and comparing each back projection error with a threshold. The testing comprises for each first point, determining a correction term based on an estimation of the depth of the first point in the first image and an estimation of the movement between the first and second images, and determining the threshold associated with the first point by using said correction term.

公开(公告)号：US10312889B2

公开(公告)日：2019-06-04

申请号：US15605541

申请日：2017-05-25

Applicant: STMicroelectronics SA

Inventor： Denis Pache ,  Stephane Le Tual ,  Hanae Zegmout

IPC: H03K3/42 ,  G06F1/10 ,  H03M1/12 ,  H01L31/08 ,  H03K3/36

Abstract: The present disclosure relates to a device for generating a clock signal including a first photoresistor coupling a capacitive output node to a node receiving a first potential. A second photoresistor couples the capacitive node to a node receiving a second potential. The first and second photoresistors receive the same optical pulses of a mode-locked laser at instants in time offset by a first delay.

公开(公告)号：US10312240B2

公开(公告)日：2019-06-04

申请号：US15868901

申请日：2018-01-11

Applicant: STMICROELECTRONICS SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78 ,  G11C11/409 ,  H01L27/108

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.