公开(公告)号：US09099348B2

公开(公告)日：2015-08-04

申请号：US13602038

申请日：2012-08-31

Applicant: Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

IPC: H01L29/76 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.

Abstract translation: 半导体器件包括：垂直沟道层; 管道沟道层，被配置为连接垂直沟道层的下端; 以及围绕所述管道沟道层的管道浇口，并且包括与所述管道沟道层接触并且包括第一类型杂质的第一区域，以及包括与所述第一类型杂质不同的第二类型杂质的剩余的第二区域。

公开(公告)号：US08878277B2

公开(公告)日：2014-11-04

申请号：US13598528

申请日：2012-08-29

Applicant: Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

IPC: H01L29/76

CPC classification number: H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.

Abstract translation: 3D非易失性存储器件包括管道浇口，至少一个第一沟道层，其包括形成在管道栅极中的第一管道沟道层，以及一对第一源极侧沟道层和与第一管道沟道连接的第一漏极侧沟道层 层，以及至少一个第二沟道层，其包括形成在管道浇口中并位于第一管道沟道层上的第二管道沟道层和连接到第二管道沟道层的一对第二源极侧沟道层和第二漏极侧沟道层 。

公开(公告)号：US08754485B2

公开(公告)日：2014-06-17

申请号：US13477632

申请日：2012-05-22

Applicant: Ki Hong Lee ,  Seung Ho Pyi ,  Sung Chul Shin

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  Sung Chul Shin

IPC: H01L21/70

CPC classification number: H01L27/115 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

Abstract: A 3-dimensional (3-D) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel and in an L shape, and a gate insulating layer interposed between the first channel and the selection gate and surrounding the first channel. A method of manufacturing a 3-D non-volatile memory device includes forming first channels protruding from a substrate, forming a first gate insulating layer surrounding the first channels, and forming first selection gates having an L shape on sidewalls of the first channels on which the first gate insulating layers are formed.

Abstract translation: 三维（3-D）非易失性存储装置包括从基板突出的第一通道，形成在第一通道的侧壁上且呈L形的选择栅极，以及插入在第一通道和第二通道之间的栅极绝缘层 选择门和围绕第一通道。 一种制造3-D非易失性存储器件的方法包括形成从衬底突出的第一通道，形成围绕第一通道的第一栅极绝缘层，以及在第一通道的侧壁上形成具有L形形状的第一选择栅极， 形成第一栅极绝缘层。

公开(公告)号：US08735962B2

公开(公告)日：2014-05-27

申请号：US13599680

申请日：2012-08-30

Applicant: Sung Jin Whang ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Min Soo Kim

Inventor： Sung Jin Whang ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Min Soo Kim

IPC: H01L29/788 ,  H01L21/20

CPC classification number: H01L27/11556 ,  H01L29/7889

Abstract: A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.

Abstract translation: 根据本发明的实施例的半导体器件包括从半导体衬底向上突出的垂直沟道层，覆盖垂直沟道层的侧壁的隧道绝缘层，彼此分离并堆叠的多个浮动栅极 沿着垂直沟道层，并且在其间插入隧道绝缘层的周围的垂直沟道层，分别包围多个浮置栅极的多个控制栅极和设置在多个控制栅极之间的层间绝缘层。

公开(公告)号：US20130168752A1

公开(公告)日：2013-07-04

申请号：US13604073

申请日：2012-09-05

Applicant: Min-Soo KIM ,  Dong-Sun SHEEN ,  Seung-Ho PYI ,  Sung-Jin WHANG

Inventor： Min-Soo KIM ,  Dong-Sun SHEEN ,  Seung-Ho PYI ,  Sung-Jin WHANG

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L27/11582

Abstract: A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.

Abstract translation: 非易失性存储器件包括：衬底，其包括表面，形成在所述衬底的表面上的从所述表面垂直突出的沟道层，以及沿所述沟道层交替堆叠的多个层间电介质层和多个栅极电极层， 其中所述多个栅极电极层从所述多个层间电介质层突出。

公开(公告)号：US20130069152A1

公开(公告)日：2013-03-21

申请号：US13234422

申请日：2011-09-16

Applicant: Ki Hong Lee ,  Seung Ho Pyi ,  II Young Kwon ,  Jin Ho Bin

Inventor： Ki Hong Lee ,  Seung Ho Pyi ,  II Young Kwon ,  Jin Ho Bin

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/66833 ,  H01L29/7926

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract translation: 公开了一种3D结构的非易失性半导体存储器件及其制造方法。 一个这样的器件包括在源极/漏极区域的n +区域; 源/漏区的p +区; 以及在n +区域和p +区域之间的扩散阻挡材料。 n +区域基本上与p +区隔离。

公开(公告)号：US20130049095A1

公开(公告)日：2013-02-28

申请号：US13599680

申请日：2012-08-30

Applicant: Sung Jin WHANG ,  Dong Sun SHEEN ,  Seung Ho PYI ,  Min Soo KIM

Inventor： Sung Jin WHANG ,  Dong Sun SHEEN ,  Seung Ho PYI ,  Min Soo KIM

IPC: H01L29/788 ,  H01L21/20

CPC classification number: H01L27/11556 ,  H01L29/7889

Abstract: A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.

Abstract translation: 根据本发明的实施例的半导体器件包括从半导体衬底向上突出的垂直沟道层，覆盖垂直沟道层的侧壁的隧道绝缘层，彼此分离并堆叠的多个浮动栅极 沿着垂直沟道层，并且在其间插入隧道绝缘层的周围的垂直沟道层，分别包围多个浮置栅极的多个控制栅极和设置在多个控制栅极之间的层间绝缘层。

公开(公告)号：US20120299117A1

公开(公告)日：2012-11-29

申请号：US13477632

申请日：2012-05-22

Applicant: Ki Hong LEE ,  Seung Ho Pyi ,  Sung Chui Shin

Inventor： Ki Hong LEE ,  Seung Ho Pyi ,  Sung Chui Shin

IPC: H01L27/088 ,  H01L21/20

CPC classification number: H01L27/115 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

Abstract: A 3-dimensional (3-D) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel and in an L shape, and a gate insulating layer interposed between the first channel and the selection gate and surrounding the first channel. A method of manufacturing a 3-D non-volatile memory device includes forming first channels protruding from a substrate, forming a first gate insulating layer surrounding the first channels, and forming first selection gates having an L shape on sidewalls of the first channels on which the first gate insulating layers are formed.

Abstract translation: 三维（3-D）非易失性存储装置包括从基板突出的第一通道，形成在第一通道的侧壁上且呈L形的选择栅极，以及插入在第一通道和第二通道之间的栅极绝缘层 选择门和围绕第一通道。 一种制造3-D非易失性存储器件的方法包括形成从衬底突出的第一通道，形成围绕第一通道的第一栅极绝缘层，以及在第一通道的侧壁上形成具有L形形状的第一选择栅极， 形成第一栅极绝缘层。

公开(公告)号：US08022501B2

公开(公告)日：2011-09-20

申请号：US12504427

申请日：2009-07-16

Applicant: Seung-Ho Pyi

Inventor： Seung-Ho Pyi

IPC: H01L21/768 ,  H01L21/70 ,  H01L23/522

CPC classification number: H01L21/76232 ,  H01L21/764 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

Abstract translation: 本发明涉及半导体器件及其分离方法。 半导体器件包括：硅衬底，其设置有在沟槽的底部具有至少一个硅柱的沟槽，其中硅柱变成微沟槽的侧壁; 以及选择性地和部分地填充到多个微沟槽中的器件隔离层。

公开(公告)号：US07968912B2

公开(公告)日：2011-06-28

申请号：US12749176

申请日：2010-03-29

Applicant: Yong-Soo Kim ,  Hong-Seon Yang ,  Seung-Ho Pyi ,  Tae-Hang Ahn

Inventor： Yong-Soo Kim ,  Hong-Seon Yang ,  Seung-Ho Pyi ,  Tae-Hang Ahn

IPC: H01L29/78 ,  H01L27/12

CPC classification number: H01L29/0847 ,  H01L21/18 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a gate formed over the substrate, a gate spacer provided against first and second sidewalls of the gate, and a source/drain region formed in the substrate proximate to the gate spacer. The source/drain region includes first and second epitaxial layers including Ge, wherein the second epitaxial layer which is formed over an interfacial layer between the first epitaxial layer and the substrate has a higher germanium concentration than that of the first epitaxial layer.

Abstract translation: 半导体器件包括衬底，形成在衬底上的栅极，设置在栅极的第一和第二侧壁上的栅极间隔，以及形成在靠近栅极间隔物的衬底中的源/漏区。 源极/漏极区包括包括Ge的第一和第二外延层，其中在第一外延层和衬底之间的界面层上形成的第二外延层具有比第一外延层更高的锗浓度。