公开(公告)号：US20120229318A1

公开(公告)日：2012-09-13

申请号：US13044619

申请日：2011-03-10

Applicant: Jun-De JIN ,  Ming Hsien TSAI ,  Tzu-Jin YEH

Inventor： Jun-De JIN ,  Ming Hsien TSAI ,  Tzu-Jin YEH

IPC: H03M1/12 ,  H03H7/01

CPC classification number: H03H7/09 ,  H03H7/075 ,  H03H7/1758 ,  H03H2001/0078

Abstract: A bandpass filter comprises a first capacitor, a second capacitor, a third capacitor and at least two resonators. The first and second capacitors are coupled in parallel with each other, and each of the first and second capacitors includes an input. The third capacitor is coupled between the first capacitor and the second capacitor at their respective inputs. The at least two resonators are coupled in parallel with the first capacitor and the second capacitor and are positioned adjacent to each other at a distance such that the at least one component of the resonators are electromagnetically coupled together to provide three (3) transmission zeros.

Abstract translation: 带通滤波器包括第一电容器，第二电容器，第三电容器和至少两个谐振器。 第一和第二电容器彼此并联耦合，并且第一和第二电容器中的每一个包括输入端。 第三电容器在它们各自的输入处耦合在第一电容器和第二电容器之间。 所述至少两个谐振器与第一电容器和第二电容器并联耦合并且以一定距离彼此相邻地定位，使得谐振器的至少一个分量电磁耦合在一起以提供三（3）个传输零点。

公开(公告)号：US20120208457A1

公开(公告)日：2012-08-16

申请号：US13028270

申请日：2011-02-16

Applicant: Jun-De JIN ,  Ming Hsien TSAI ,  Tzu-Jin YEH

Inventor： Jun-De JIN ,  Ming Hsien TSAI ,  Tzu-Jin YEH

IPC: H04B5/00

CPC classification number: H01L25/0657 ,  H01L23/48 ,  H01L23/645 ,  H01L2225/06531 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01Q1/2283 ,  H01L2924/00

Abstract: A multi-chip module includes a chip stack package including at least one pair of stacked dies, the dies having overlapping opposing faces, and at least one capacitive proximity communication (CPC) interconnect between the pair of stacked dies. The CPC interconnect includes a first capacitor plate at a first one of the overlapping opposing faces and a second capacitor plate at a second one of the overlapping opposing faces spaced from and aligned with the first capacitor plate. The CPC interconnect further includes an inductive element connected in series with the first capacitor plate and second capacitor plate, wherein the capacitor plates form part of a capacitor and the capacitor cooperates with the inductor element to form a LC circuit having a resonant frequency.

Abstract translation: 多芯片模块包括芯片堆叠封装，其包括至少一对堆叠的裸片，所述裸片具有重叠的相对面，以及在所述一对堆叠裸片之间的至少一个电容邻近通信（CPC）互连。 CPC互连包括在重叠相对面中的第一个处的第一电容器板和与第一电容器板间隔开并与第一电容器板对准的第二个重叠相对面中的第二电容器板。 CPC互连还包括与第一电容器板和第二电容器板串联连接的电感元件，其中电容器板形成电容器的一部分，并且电容器与电感器元件配合以形成具有谐振频率的LC电路。

公开(公告)号：US08193880B2

公开(公告)日：2012-06-05

申请号：US12023184

申请日：2008-01-31

Applicant: Shu-Ying Cho ,  Tzu-Jin Yeh ,  Sally Liu

Inventor： Shu-Ying Cho ,  Tzu-Jin Yeh ,  Sally Liu

IPC: H03H7/38 ,  H01P3/08

CPC classification number: H01P3/003 ,  H01P3/06 ,  H05K1/0219 ,  H05K1/0242 ,  H05K1/025 ,  H05K2201/09236 ,  H05K2201/09727 ,  H05K2201/09781

Abstract: A semiconductor device for transmitting a radio frequency signal along a signal line includes a signal line that extends along a principal axis. On one side of the signal line is a first dielectric, and on the opposite side of the signal line is a second dielectric. First and second ground lines are proximate to the first and second dielectrics, respectively, and the ground lines are approximately parallel to the signal line. The device has a transverse cross-section that varies along the principal axis.

Abstract translation: 沿着信号线发送射频信号的半导体装置包括沿主轴延伸的信号线。 在信号线的一侧是第一电介质，信号线的相对侧是第二电介质。 第一和第二接地线分别靠近第一和第二电介质，并且接地线近似平行于信号线。 该装置具有沿主轴变化的横截面。

公开(公告)号：US07954080B2

公开(公告)日：2011-05-31

申请号：US12042606

申请日：2008-03-05

Applicant: Hsiao-Tsung Yen ,  Tzu-Jin Yeh ,  Sally Liu

Inventor： Hsiao-Tsung Yen ,  Tzu-Jin Yeh ,  Sally Liu

IPC: G06F17/50

CPC classification number: G01R31/2884 ,  H01L22/34

Abstract: A method and system for de-embedding an on-wafer device is disclosed. The method comprises representing the intrinsic characteristics of a test structure using a set of ABCD matrix components; determining the intrinsic characteristics arising from the test structure; and using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”).

Abstract translation: 公开了一种用于去嵌入晶片装置的方法和系统。 该方法包括使用一组ABCD矩阵分量表示测试结构的固有特性; 确定测试结构产生的内在特性; 并且使用确定的测试结构的固有特性来产生表示待测器件（“DUT”）的固有特性的一组参数。

公开(公告)号：US06989578B2

公开(公告)日：2006-01-24

申请号：US10632456

申请日：2003-07-31

Applicant: Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

Inventor： Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

IPC: H01L29/41

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: An inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type and at least two deep wells of opposite conductivity type in the substrate underneath the track. In another embodiment, an inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type; a shallow trench isolation region formed in the substrate underneath the trace; and at least two deep wells of opposite conductivity type in the substrate underneath the shallow trench isolation region. The present invention also includes methods of manufacturing the aforementioned inductors.

Abstract translation: 集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在轨道下方的衬底中的第一导电类型的半导体衬底和相反导电类型的至少两个深阱。 在另一个实施例中，集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在第一导电类型的半导体衬底上; 在轨迹下方的衬底中形成的浅沟槽隔离区域; 以及在浅沟槽隔离区域下方的衬底中具有相反导电类型的至少两个深阱。 本发明还包括制造上述电感器的方法。

公开(公告)号：US6114209A

公开(公告)日：2000-09-05

申请号：US45102

申请日：1998-03-19

Applicant: Chih-Hsun Chu ,  Tzu-Jin Yeh

Inventor： Chih-Hsun Chu ,  Tzu-Jin Yeh

IPC: H01L21/285 ,  H01L21/336 ,  H01L29/417

CPC classification number: H01L29/6659 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device with raised source/drain. This method eliminates the problem which is often experienced when the shallow junction technique is applied, in which over-etching of the source/drain region during the contact etching and the salicide process can lead to current leakages. The improved method includes the steps of forming a buffer conductive blocks on the source/drain regions which increase the thickness of source/drain regions. A related semiconductor structure made by the method has a plurality of bi-flange shape side wall spacers by which the semiconductor structure not only elevates the doped regions, it also provides an improved capability to suppress the electric bridges between the gate electrode and source/drain regions, respectively.

Abstract translation: 一种制造具有升高的源极/漏极的半导体器件的方法。 该方法消除了当应用浅结技术时经常遇到的问题，其中在接触蚀刻和自对准处理过程中源极/漏极区域的过度蚀刻可导致电流泄漏。 改进的方法包括以下步骤：在源/漏区上形成缓冲导电块，增加源极/漏极区的厚度。 通过该方法制造的相关半导体结构具有多个双凸缘形状的侧壁间隔件，通过该多个双凸缘形状的侧壁间隔件，半导体结构不仅提高了掺杂区域，而且还提供了改善的能力，以抑制栅电极和源极/漏极 区域。