公开(公告)号：US20120037910A1

公开(公告)日：2012-02-16

申请号：US13111027

申请日：2011-05-19

Applicant: Young-Joo CHOI ,  Woo-Geun LEE ,  Do-Hyun KIM

Inventor： Young-Joo CHOI ,  Woo-Geun LEE ,  Do-Hyun KIM

IPC: H01L33/08 ,  H01L33/16

CPC classification number: H01L27/1225

Abstract: A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode.

Abstract translation: 显示基板包括： 栅极图案，包括设置在基板上的栅极电极，设置在基板上的栅极绝缘层和栅极图案，绝缘图案，包括： 设置在与栅电极重叠的栅极绝缘层的第一区域上的第一厚度部分和设置在与第一区域相邻的栅极绝缘层的第二区域上的第二厚度部分，设置在栅极绝缘层的第一厚度部分上的氧化物半导体图案 第一区域，设置在氧化物半导体图案上的蚀刻停止件，包括与氧化物半导体图案接触的源电极和漏电极的源图案以及与漏电极接触的像素电极。

公开(公告)号：US08022411B2

公开(公告)日：2011-09-20

申请号：US12499009

申请日：2009-07-07

Applicant: Kap-Soo Yoon ,  Ki-Won Kim ,  Sung-Ryul Kim ,  Sung-Hoon Yang ,  Woo-Geun Lee

Inventor： Kap-Soo Yoon ,  Ki-Won Kim ,  Sung-Ryul Kim ,  Sung-Hoon Yang ,  Woo-Geun Lee

IPC: H01L51/52

CPC classification number: H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/7869

Abstract: Provided are a thin-film transistor (TFT) display panel having improved electrical properties that can be fabricated time-effectively and a method of fabricating the TFT display panel. The TFT display panel includes: gate wirings which are formed on an insulating substrate; oxide active layer patterns which are formed on the gate wirings; data wirings which are formed on the oxide active layer patterns to cross the gate wirings; a passivation layer which is formed on the oxide active layer patterns and the data wirings and is made of silicon nitride (SiNx); and a pixel electrode which is formed on the passivation layer.

Abstract translation: 提供了一种薄膜晶体管（TFT）显示面板，其具有可以有效制造的改进的电气特性，以及制造TFT显示面板的方法。 TFT显示面板包括：形成在绝缘基板上的栅极布线; 形成在栅极布线上的氧化物有源层图案; 形成在氧化物有源层图案上以跨过栅极布线的数据布线; 形成在氧化物有源层图案和数据布线上并由氮化硅（SiNx）制成的钝化层; 以及形成在钝化层上的像素电极。

公开(公告)号：US20110193076A1

公开(公告)日：2011-08-11

申请号：US12957743

申请日：2010-12-01

Applicant: Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20110159622A1

公开(公告)日：2011-06-30

申请号：US13042348

申请日：2011-03-07

Applicant: Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

Inventor： Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

IPC: H01L33/62

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/66765

Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

公开(公告)号：US07923732B2

公开(公告)日：2011-04-12

申请号：US12331361

申请日：2008-12-09

Applicant: Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

Inventor： Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

IPC: H01L29/00

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/66765

Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

公开(公告)号：US07834676B2

公开(公告)日：2010-11-16

申请号：US12357261

申请日：2009-01-21

Applicant: Woo-Geun Lee ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

Inventor： Woo-Geun Lee ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

IPC: G11C11/34

CPC classification number: G09G3/3648 ,  G09G2300/0413 ,  G09G2300/0819 ,  G09G2320/043

Abstract: A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.

Abstract translation: 提出了一种用于考虑晶体管特性变化的装置。 该器件包括晶体管和比较器，其接收来自晶体管的反馈信号和参考信号。 比较器向偏置电压发生器提供输出。 偏置电压发生器包括连接到比较器的输出的输入端和连接到晶体管的输出。 在本发明的一些实施例中，晶体管是双栅极晶体管，并且偏置电压发生器被施加到双栅晶体管的顶栅，以便控制晶体管的特性，例如导通电压。

公开(公告)号：US20100182068A1

公开(公告)日：2010-07-22

申请号：US12357261

申请日：2009-01-21

Applicant: Woo-Geun LEE ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

Inventor： Woo-Geun LEE ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

IPC: G06G7/12

CPC classification number: G09G3/3648 ,  G09G2300/0413 ,  G09G2300/0819 ,  G09G2320/043

Abstract: A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.

Abstract translation: 提出了一种用于考虑晶体管特性变化的装置。 该器件包括晶体管和比较器，其接收来自晶体管的反馈信号和参考信号。 比较器向偏置电压发生器提供输出。 偏置电压发生器包括连接到比较器的输出的输入端和连接到晶体管的输出。 在本发明的一些实施例中，晶体管是双栅极晶体管，并且偏置电压发生器被施加到双栅晶体管的顶栅，以便控制晶体管的特性，例如导通电压。

公开(公告)号：US20100079710A1

公开(公告)日：2010-04-01

申请号：US12408213

申请日：2009-03-20

Applicant: Byung-Duk Yang ,  Jang-Soo Kim ,  Woo-Geun Lee ,  Ki-Won Kim ,  Sang-Ki Kwak ,  Hyang-Shik Kong ,  Sang-Hun Lee

Inventor： Byung-Duk Yang ,  Jang-Soo Kim ,  Woo-Geun Lee ,  Ki-Won Kim ,  Sang-Ki Kwak ,  Hyang-Shik Kong ,  Sang-Hun Lee

IPC: G02F1/1335 ,  G02F1/1333 ,  G02F1/13

CPC classification number: G02F1/136204 ,  G02F1/13392 ,  G02F1/1341 ,  G02F2001/133388

Abstract: A display substrate includes a transistor layer, a plurality of color filters, a first blocking member, a supporting member, a circuit part, a second blocking member and a protruding member. The first blocking member is disposed between different color filters. The supporting member maintains a distance between a base substrate and a substrate facing the base substrate. A circuit part is disposed in a peripheral area surrounding a display area, and the circuit part includes a metal pattern and a contact electrode in contact with the metal pattern. The second blocking member includes substantially the same material as the first blocking member and the second blocking member covers the circuit part. The protruding member includes substantially the same material as the second blocking member, and is integrally formed with the second blocking member.

Abstract translation: 显示基板包括晶体管层，多个滤色器，第一阻挡构件，支撑构件，电路部分，第二阻挡构件和突出构件。 第一阻挡构件设置在不同的滤色器之间。 支撑构件保持基底基板和面向基底基板的基板之间的距离。 电路部分设置在围绕显示区域的周边区域中，并且电路部分包括与金属图案接触的金属图案和接触电极。 第二阻挡构件包括与第一阻挡构件基本相同的材料，并且第二阻挡构件覆盖电路部分。 突出构件包括与第二阻挡构件基本相同的材料，并且与第二阻挡构件一体地形成。

公开(公告)号：US20080203393A1

公开(公告)日：2008-08-28

申请号：US12099718

申请日：2008-04-08

Applicant: Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

Inventor： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC: H01L27/088

CPC classification number: H01L27/124 ,  G02F2001/13629 ,  H01L29/458

Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

Abstract translation: 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US07172913B2

公开(公告)日：2007-02-06

申请号：US11082967

申请日：2005-03-18

Applicant: Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

Inventor： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC: H01L21/00

CPC classification number: H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

Abstract: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。