公开(公告)号：US08405160B2

公开(公告)日：2013-03-26

申请号：US12787972

申请日：2010-05-26

申请人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

发明人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

IPC分类号： H01L27/088 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源极/漏极结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度与第一接近度不同。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

公开(公告)号：US08096132B2

公开(公告)日：2012-01-17

申请号：US12034064

申请日：2008-02-20

申请人： Yimin Huang ,  Shaun Sullivan ,  Brian Finstad ,  Alexander Haplau-Colan

发明人： Yimin Huang ,  Shaun Sullivan ,  Brian Finstad ,  Alexander Haplau-Colan

IPC分类号： F02C1/00 ,  F02G3/00

CPC分类号： F23R3/14 ,  F23R3/283 ,  F23R3/286 ,  F23R3/46

摘要： A combustor for a gas turbine engine is disclosed which is able to operate with high combustion efficiency, and low nitrous oxide emissions during gas turbine operations. The combustor consists of a can-type configuration which combusts fuel premixed with air and delivers the hot gases to a turbine. Fuel is premixed with air through a swirler and is delivered to the combustor with a high degree of swirl motion about a central axis. This swirling mixture of reactants is conveyed downstream through a flow path that expands; the mixture reacts, and establishes an upstream central recirculation flow along the central axis. A cooling assembly is located on the swirler co-linear with the central axis in which cooler air is conveyed into the prechamber between the recirculation flow and the swirler surface.

摘要翻译： 公开了一种用于燃气涡轮发动机的燃烧器，其能够在燃气轮机操作期间以高燃烧效率和低氧化亚氮排放进行操作。 燃烧器由罐型构成，其燃烧与空气预混合的燃料并将热气体输送到涡轮机。 燃料通过旋流器与空气预混合并且以围绕中心轴线的高度漩涡运动输送到燃烧器。 反应物的这种旋转混合物通过膨胀的流动路径向下游传送; 混合物反应，并建立沿中心轴的上游中央再循环流。 冷却组件位于与中心轴线共线的旋流器上，其中较冷的空气被输送到再循环流和旋流器表面之间的预燃室中。

公开(公告)号：US20090205339A1

公开(公告)日：2009-08-20

申请号：US12034064

申请日：2008-02-20

申请人： Yimin Huang ,  Shaun Sullivan ,  Brian Finstad ,  Alexander Haplau-Colan

发明人： Yimin Huang ,  Shaun Sullivan ,  Brian Finstad ,  Alexander Haplau-Colan

IPC分类号： F23R3/28 ,  F23R3/14 ,  F02C7/22

CPC分类号： F23R3/14 ,  F23R3/283 ,  F23R3/286 ,  F23R3/46

摘要： A combustor for a gas turbine engine is disclosed which is able to operate with high combustion efficiency, and low nitrous oxide emissions during gas turbine operations. The combustor consists of a can-type configuration which combusts fuel premixed with air and delivers the hot gases to a turbine. Fuel is premixed with air through a swirler and is delivered to the combustor with a high degree of swirl motion about a central axis. This swirling mixture of reactants is conveyed downstream through a flow path that expands; the mixture reacts, and establishes an upstream central recirculation flow along the central axis. A cooling assembly is located on the swirler co-linear with the central axis in which cooler air is conveyed into the prechamber between the recirculation flow and the swirler surface.

摘要翻译： 公开了一种用于燃气涡轮发动机的燃烧器，其能够在燃气轮机操作期间以高燃烧效率和低氧化亚氮排放进行操作。 燃烧器由罐型构成，其燃烧与空气预混合的燃料并将热气体输送到涡轮机。 燃料通过旋流器与空气预混合并且以围绕中心轴线的高度漩涡运动输送到燃烧器。 反应物的这种旋转混合物通过膨胀的流动路径向下游传送; 混合物反应，并建立沿中心轴的上游中央再循环流。 冷却组件位于与中心轴线共线的旋流器上，其中较冷的空气被输送到再循环流和旋流器表面之间的预燃室中。

公开(公告)号：US06617234B2

公开(公告)日：2003-09-09

申请号：US09835014

申请日：2001-04-13

申请人： Sung-Hsiung Wang ,  Yimin Huang ,  Chiung-Sheng Hsiung

发明人： Sung-Hsiung Wang ,  Yimin Huang ,  Chiung-Sheng Hsiung

IPC分类号： H01L2144

CPC分类号： H01L24/02 ,  H01L23/5256 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  Y10S438/978

摘要： A method of forming metal fuses and bonding pads. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.

摘要翻译： 一种形成金属熔断器和焊盘的方法。 在衬底中形成导电层。 介电层形成在衬底上。 电介质层具有露出导电层的一部分的开口。 在电介质层上形成金属层。 将金属层图案化以形成金属熔丝和接合焊盘。 接合焊盘经由开口电连接到导电层。 金属保险丝和接合垫都有底切的侧壁。 垫片形成在金属保险丝和接合垫的底切侧壁上。 最后，在衬底上形成暴露金属熔丝和焊盘的钝化层。

公开(公告)号：US06268283B1

公开(公告)日：2001-07-31

申请号：US09248159

申请日：1999-02-09

申请人： Yimin Huang

发明人： Yimin Huang

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： An improved method for forming a dual damascene structure is described. A via opening of the dual damascene structure is formed in a dielectric layer. A non-conformal cap layer is then formed on the substrate before the step of defining the photoresist layer. The non-conformal cap layer only covers the top region of the trench but does not fill the trench. A patterned photoresist layer is then formed on the substrate followed by an etching procedure so as to form a trench. The photoresist layer is then removed. The trench and via opening are filled with a conductive layer. Thereafter, redundant portions of the conductive layer are removed by a planarization process.

摘要翻译： 描述了用于形成双镶嵌结构的改进方法。 电介质层中形成双镶嵌结构的通孔。 然后在限定光致抗蚀剂层的步骤之前，在基板上形成非保形盖层。 非保形盖层仅覆盖沟槽的顶部区域，但不填充沟槽。 然后在衬底上形成图案化的光致抗蚀剂层，然后进行蚀刻程序以形成沟槽。 然后除去光致抗蚀剂层。 沟槽和通孔开口填充有导电层。 此后，通过平坦化处理去除导电层的冗余部分。

公开(公告)号：US06251694B1

公开(公告)日：2001-06-26

申请号：US09318597

申请日：1999-05-26

申请人： Hermen Liu ,  Yimin Huang

发明人： Hermen Liu ,  Yimin Huang

IPC分类号： H01L3126

CPC分类号： H01L22/20 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/00

摘要： The present invention provides a method of testing and packaging a semiconductor chip. The semiconductor chip includes an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC. The method includes using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC, and forming a passivation layer on the surface of the semiconductor chip to passivate the surface of the semiconductor chip. The testing area of the bonding pad is covered under the passivation layer and the passivation layer has an opening positioned on the bonding pad outside the testing area which is used as a connecting area for performing wire bonding or bumping.

摘要翻译： 本发明提供一种测试和封装半导体芯片的方法。 半导体芯片包括位于半导体芯片内的集成电路（IC）和位于半导体芯片的表面上且与IC电连接的接合焊盘。 该方法包括使用探针接触焊盘表面上的预定测试区域以对IC进行电测试，以及在半导体芯片的表面上形成钝化层以钝化半导体芯片的表面。 接合焊盘的测试区域被覆​​盖在钝化层下方，并且钝化层具有位于测试区域外部的焊盘上的开口，该开口用作用于进行引线接合或凸起的连接区域。

公开(公告)号：US06191028B1

公开(公告)日：2001-02-20

申请号：US09059751

申请日：1998-04-14

申请人： Yimin Huang ,  Tri-Rung Yew

发明人： Yimin Huang ,  Tri-Rung Yew

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76811

摘要： A method of patterning a dielectric layer. On a substrate having a metal wiring layer formed thereon, a dielectric layer and a masking layer are formed. A cap insulation layer is formed on the masking layer before patterning the dielectric layer. In addition, a dual damasecence process is used for patterning the dielectric layer.

摘要翻译： 图案化介电层的方法。 在其上形成有金属布线层的基板上，形成介电层和掩模层。 在图案化电介质层之前，在掩模层上形成帽绝缘层。 此外，使用双重破坏过程来对介电层进行图案化。

公开(公告)号：US6156648A

公开(公告)日：2000-12-05

申请号：US265207

申请日：1999-03-10

申请人： Yimin Huang

发明人： Yimin Huang

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76843

摘要： A method for fabricating a dual damascene structure. A cap layer and a dielectric layer are formed in sequence over a substrate having a first conductive layer. A trench and a via hole are formed in the dielectric layer. The via hole is aligned under the trench. A barrier spacer is formed on sidewalls of the trench and the via hole. The cap layer exposed by the via hole is removed. A conformal adhesion layer is formed over the substrate. A second conductive layer is formed over the substrate and fills the trench and the via hole. A portion of the second conductive layer and the adhesion layer are removed to expose the dielectric layer.

摘要翻译： 一种制造双镶嵌结构的方法。 在具有第一导电层的衬底上依次形成覆盖层和电介质层。 在电介质层中形成沟槽和通孔。 通孔在沟槽下对齐。 在沟槽和通孔的侧壁上形成阻挡隔离物。 由通孔露出的盖层被去除。 在衬底上形成共形粘附层。 第二导电层形成在衬底上并填充沟槽和通孔。 去除第二导电层和粘附层的一部分以暴露电介质层。

公开(公告)号：US6077769A

公开(公告)日：2000-06-20

申请号：US72311

申请日：1998-05-04

申请人： Yimin Huang ,  Tony Lin ,  Tri-Rung Yew

发明人： Yimin Huang ,  Tony Lin ,  Tri-Rung Yew

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76811

摘要： A method is provided for fabricating a dual damascene structure on a substrate with a first dielectric layer, an etching stop layer, a second dielectric layer, and a hard mask layer formed on it. The first step is to define the hard mask layer in order to form the first hole, which corresponds to the position of the conductive layer exposing the second dielectric layer. Then, an etching process, including an etching step with medium SiO.sub.2 /SiN etching selectivity and an over-etching step with high SiO.sub.2 /SiN etching selectivity, is performed to form the second hole and the third hole. Finally, a glue/barrier layer and a metal layer are filled into the second hole and the third hole, thus accomplishing a dual damascene structure.

摘要翻译： 提供了一种用于在衬底上制造双镶嵌结构的方法，其上形成有第一介电层，蚀刻停止层，第二介电层和硬掩模层。 第一步是定义硬掩模层以形成第一孔，其对应于暴露第二电介质层的导电层的位置。 然后，进行包括具有中等SiO 2 / SiN蚀刻选择性的蚀刻步骤和具有高SiO 2 / SiN蚀刻选择性的过蚀刻步骤的蚀刻工艺，以形成第二孔和第三孔。 最后，将胶/阻挡层和金属层填充到第二孔和第三孔中，从而实现双镶嵌结构。

公开(公告)号：US6025264A

公开(公告)日：2000-02-15

申请号：US52608

申请日：1998-03-31

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun ,  Yimin Huang

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun ,  Yimin Huang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC分类号： H01L21/76843 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

摘要翻译： 一种用于形成阻挡层的方法，包括以下步骤：首先提供其上已经形成有导电层的半导体衬底。 然后，在导电层和半导体衬底上沉积诸如有机低k电介质层的电介质层。 接下来，形成在暴露导电层的电介质层中的开口。 此后，第一阻挡层沉积到开口和周围区域中。 第一阻挡层可以是通过等离子体增强化学气相沉积（PECVD）法，低压化学气相沉积法（LPCVD）法，电子束 蒸发法或溅射法。 最后，在第一阻挡层上形成第二阻挡层。 第二阻挡层可以是钛/氮化钛（Ti / TiN）层，氮化钨（WN）层，钽（Ta）层或氮化钽（TaN）层。