公开(公告)号：US07968968B2

公开(公告)日：2011-06-28

申请号：US12790526

申请日：2010-05-28

申请人： Sung-Hsiung Wang ,  Chih-Ping Chao ,  Chia-Yu Su

发明人： Sung-Hsiung Wang ,  Chih-Ping Chao ,  Chia-Yu Su

IPC分类号： H01L27/08

CPC分类号： H01L28/10

摘要： An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.

摘要翻译： 一种利用垫金属层的电感器。 电感器包括金属螺旋，金属桥和金属互连。 金属桥形成有焊盘金属层和多个通孔，并且一端连接到金属螺旋。 金属互连连接到金属桥的另一端。 此外，焊垫金属层的电阻率低于金属螺旋的电阻率。

公开(公告)号：US20100265025A1

公开(公告)日：2010-10-21

申请号：US12790526

申请日：2010-05-28

申请人： Sung-Hsiung Wang ,  Chih-Ping Chao ,  Chia-Yu Su

发明人： Sung-Hsiung Wang ,  Chih-Ping Chao ,  Chia-Yu Su

IPC分类号： H01F5/00

CPC分类号： H01L28/10

摘要： An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.

摘要翻译： 一种利用垫金属层的电感器。 电感器包括金属螺旋，金属桥和金属互连。 金属桥形成有焊盘金属层和多个通孔，并且一端连接到金属螺旋。 金属互连连接到金属桥的另一端。 此外，焊垫金属层的电阻率低于金属螺旋的电阻率。

公开(公告)号：US07074721B2

公开(公告)日：2006-07-11

申请号：US10407082

申请日：2003-04-03

申请人： Sung-Hsiung Wang

发明人： Sung-Hsiung Wang

IPC分类号： H01L21/302

CPC分类号： H01L21/76843 ,  H01L21/2885 ,  H01L21/76808 ,  H01L21/76832 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2221/1031

摘要： A method for forming a void free ultra thick dual damascene copper feature providing a semiconductor process wafer comprising via openings formed in a first undoped silicate glass (USG) layer the first USG layer having an overlying a second USG layer formed having a thickness of greater than about 1 micron and an overlying silicon oxynitride BARC layer; forming a trench opening having a width of greater than about 1 micron to encompass one of the via openings; forming a barrier layer to line the dual damascene opening; forming a copper seed layer having a thickness of from about 1000 Angstroms to about 2000 Angstroms; carrying out a multi-step electrochemical deposition (ECD); and, carrying out a two step copper annealing process.

摘要翻译： 一种形成无空隙的超厚双镶嵌铜特征的方法，提供半导体工艺晶片，其包括形成在第一未掺杂硅酸盐玻璃（USG）层中的通孔，第一USG层具有覆盖第二USG层，第二USG层具有大于 约1微米和覆盖氮氧化硅BARC层; 形成具有大于约1微米宽度的沟槽开口以包围所述通路孔中的一个; 形成阻挡层以对齐双镶嵌开口; 形成厚度为约1000埃至约2000埃的铜籽晶层; 进行多步电化学沉积（ECD）; 并进行两步铜退火处理。

公开(公告)号：US07038266B2

公开(公告)日：2006-05-02

申请号：US10791246

申请日：2004-03-01

申请人： Sung Hsiung Wang

发明人： Sung Hsiung Wang

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/55 ,  H01L21/76807

摘要： A microelectronic product and a method for fabricating the same each provide a capacitor formed interposed between a first dielectric layer and a second dielectric layer formed over a substrate having a first contact region and a second contact region exposed therein. The capacitor is also connected to a first conductor stud that penetrate4s the first dielectric layer and contacts the first contact region and a second conductor stud that penetrates the second dielectric layer. A contiguous conductor interconnect and conductor stud layer is formed within a dual damascene aperture through the second dielectric layer and the first dielectric layer and contacting the second contact region. An etch stop layer employed when forming a trench within the dual damascene aperture also passivates a capacitor sidewall.

摘要翻译： 微电子产品及其制造方法各自提供了形成在第一介电层和形成在其上露出有第一接触区域和第二接触区域的基板上形成的第二电介质层之间的电容器。 电容器还连接到穿透第一介电层并接触第一接触区域的第一导体柱和穿过第二介电层的第二导体柱。 在双镶嵌孔内通过第二介电层和第一介电层形成连接的导体互连和导体柱层，并与第二接触区接触。 当在双镶嵌孔口内形成沟槽时采用的蚀刻停止层也钝化电容器侧壁。

公开(公告)号：US06559004B1

公开(公告)日：2003-05-06

申请号：US10011760

申请日：2001-12-11

申请人： Gwo-Shii Yang ,  Hsueh-Chung Chen ,  Chiung-Sheng Hsiung ,  Tong-Yu Chen ,  Sung-Hsiung Wang

发明人： Gwo-Shii Yang ,  Hsueh-Chung Chen ,  Chiung-Sheng Hsiung ,  Tong-Yu Chen ,  Sung-Hsiung Wang

IPC分类号： H01L21336

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.

摘要翻译： 一种用于形成具有垂直电容器而不是水平电容器的三维半导体结构的方法。 该方法基本上至少包括在电介质层内形成底板的这些步骤，在底板上形成另一电介质层，在底板上移除所有电介质层，在底板上形成可选的衬垫和电容器电介质层，以及形成顶板 电容电介质层。 注意，底板的形状与底部连接和垂直手指相同，还注意到底板中的每个间隙都由电容器介电层和顶板填充。

公开(公告)号：US06583489B2

公开(公告)日：2003-06-24

申请号：US10103835

申请日：2002-03-25

申请人： Sung-Hsiung Wang ,  Yi-Min Huang ,  Gwo-Shii Yang ,  Chiung-Sheng Hsiung ,  Hsueh-Chung Chen ,  Chih-Chien Liu

发明人： Sung-Hsiung Wang ,  Yi-Min Huang ,  Gwo-Shii Yang ,  Chiung-Sheng Hsiung ,  Hsueh-Chung Chen ,  Chih-Chien Liu

IPC分类号： H01L2900

CPC分类号： H01L21/76802 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/318 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

摘要： The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

公开(公告)号：US06417096B1

公开(公告)日：2002-07-09

申请号：US09611738

申请日：2000-07-07

申请人： Anseime Chen ,  Jun Maeda ,  Sheng-Yueh Chang ,  Sung-Hsiung Wang

发明人： Anseime Chen ,  Jun Maeda ,  Sheng-Yueh Chang ,  Sung-Hsiung Wang

IPC分类号： H01L214763

CPC分类号： H01L21/76826 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76807

摘要： A substrate is provided. A first dielectric layer is formed over the substrate by deposition. Etching stop layer and a second dielectric layer are formed in turn over the first dielectric. Next, the second dielectric layer is dealt with Lewis acid. Then, a first photoresist layer is defined and formed over the second dielectric layer. And then dry etching is carried out by means of the first photoresist layer as the mask to form a via hole. The surface of the second dielectric layer and the via hole are treated with Lewis acid. Subsequently, the second photoresist layer is defined and formed on the second dielectric layer. Dry etching is proceed, and etching stop layer is as a etching terminal point to remove exposed partial surface of the second dielectric layer so as to form a trench having larger horizontal size than the via hole. Subsequently, the second photoresist layer is removed to form the opening of the damascene.

摘要翻译： 提供基板。 通过沉积在衬底上形成第一介电层。 蚀刻停止层和第二介电层依次形成在第一电介质上。 接下来，第二介电层被处理路易斯酸。 然后，在第二介电层上限定并形成第一光致抗蚀剂层。 然后通过第一光致抗蚀剂层作为掩模进行干蚀刻以形成通孔。 用路易斯酸处理第二介电层和通孔的表面。 随后，第二光致抗蚀剂层被限定并形成在第二介电层上。 进行干蚀刻，并且蚀刻停止层作为蚀刻终点以去除第二电介质层的暴露的部分表面，以形成具有比通孔更大的水平尺寸的沟槽。 随后，去除第二光致抗蚀剂层以形成大马士革的开口。

公开(公告)号：US07297629B2

公开(公告)日：2007-11-20

申请号：US10942555

申请日：2004-09-15

申请人： Sung-Hsiung Wang

发明人： Sung-Hsiung Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/76813 ,  H01L21/76816

摘要： Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.

摘要翻译： 新型双镶嵌方法的特点是循环时间短，成本低。 在一个实施例中，该方法包括在衬底上提供介电层; 蚀刻电介质层中的通孔; 用诸如铜的导电金属填充通孔; 在所述通孔上提供第二电介质层; 蚀刻第二介电层中的沟槽; 并用诸如铜的导电金属填充沟槽。 在另一个实施例中，该方法包括在衬底上提供介电层; 蚀刻介电层中的部分通孔; 在部分通孔上蚀刻电介质层中的部分沟槽; 在单个蚀刻步骤中完成通孔和沟槽; 并用导电金属如铜填充通孔和沟槽，以分别完成通路和金属线。

公开(公告)号：US07229879B2

公开(公告)日：2007-06-12

申请号：US11286999

申请日：2005-11-22

申请人： Sung Hsiung Wang

发明人： Sung Hsiung Wang

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/55 ,  H01L21/76807

摘要： A microelectronic product and a method for fabricating the same each provide a capacitor formed interposed between a first dielectric layer and a second dielectric layer formed over a substrate having a first contact region and a second contact region exposed therein. The capacitor is also connected to a first conductor stud that penetrates the first dielectric layer and contacts the first contact region and a second conductor stud that penetrates the second dielectric layer. A contiguous conductor interconnect and conductor stud layer is formed within a dual damascene aperture through the second dielectric layer and the first dielectric layer and contacting the second contact region. An etch stop layer employed when forming a trench within the dual damascene aperture also passivates a capacitor sidewall.

摘要翻译： 微电子产品及其制造方法各自提供了形成在第一介电层和形成在其上露出有第一接触区域和第二接触区域的基板上形成的第二电介质层之间的电容器。 电容器还连接到穿透第一介电层并接触第一接触区域的第一导体柱和穿过第二介电层的第二导体柱。 在双镶嵌孔内通过第二介电层和第一介电层形成连接的导体互连和导体柱层，并与第二接触区接触。 当在双镶嵌孔口内形成沟槽时采用的蚀刻停止层也钝化电容器侧壁。

公开(公告)号：US20060057842A1

公开(公告)日：2006-03-16

申请号：US10942555

申请日：2004-09-15

申请人： Sung-Hsiung Wang

发明人： Sung-Hsiung Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/76813 ,  H01L21/76816

摘要： Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.

摘要翻译： 新型双镶嵌方法的特点是循环时间短，成本低。 在一个实施例中，该方法包括在衬底上提供介电层; 蚀刻电介质层中的通孔; 用诸如铜的导电金属填充通孔; 在所述通孔上提供第二电介质层; 蚀刻第二介电层中的沟槽; 并用诸如铜的导电金属填充沟槽。 在另一个实施例中，该方法包括在衬底上提供介电层; 蚀刻介电层中的部分通孔; 在部分通孔上蚀刻电介质层中的部分沟槽; 在单个蚀刻步骤中完成通孔和沟槽; 并用导电金属如铜填充通孔和沟槽，以分别完成通路和金属线。