公开(公告)号：US20080290446A1

公开(公告)日：2008-11-27

申请号：US12123817

申请日：2008-05-20

申请人： Dong-suk Shin ,  Il-young Yoon ,  Yong-kuk Jeong ,  Jung-shik Heo

发明人： Dong-suk Shin ,  Il-young Yoon ,  Yong-kuk Jeong ,  Jung-shik Heo

IPC分类号： H01L23/58 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed.

摘要翻译： 半导体器件包括覆盖沟槽的内壁，侧壁氧化物层上的氮化物衬垫和填充氮化物衬垫上的沟槽的间隙填充绝缘层的侧壁氧化物层。 第一杂质掺杂氧化物层设置在侧壁氧化物层的两个端部的边缘区域处，以便从邻近衬底的上表面的沟槽的入口延伸到氮化物衬垫。 凹槽填充绝缘层设置在沟槽中的氮化物衬垫上，以保护第一掺杂杂质的氧化物层的表面。 还公开了相关方法。

公开(公告)号：US07435654B2

公开(公告)日：2008-10-14

申请号：US11452828

申请日：2006-06-14

申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L21/20 ,  H01L21/44

CPC分类号： H01L28/40 ,  H01L21/31637 ,  H01L21/31645

摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

摘要翻译： 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层为 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

公开(公告)号：US20080218936A1

公开(公告)日：2008-09-11

申请号：US12153306

申请日：2008-05-16

申请人： Seok-Jun Won ,  Yong-Kuk Jeong

发明人： Seok-Jun Won ,  Yong-Kuk Jeong

IPC分类号： H01G4/005

CPC分类号： H01L28/60

摘要： Analog capacitors, and methods of fabricating the same, include a lower electrode having a lower conductive layer, a capacitor dielectric layer on the lower conductive layer, and an upper electrode on the capacitor dielectric layer to be opposite to the lower electrode, wherein the upper electrode includes at least an upper conductive layer in contact with the capacitor dielectric layer, wherein the upper conductive layer has a resistivity higher than that of the lower conductive layer.

摘要翻译： 模拟电容器及其制造方法包括具有下导电层的下电极，下导电层上的电容器电介质层和电容器电介质层上的与下电极相对的上电极，其中上电极 电极包括至少与电容器介电层接触的上导电层，其中上导电层的电阻率高于下导电层的电阻率。

公开(公告)号：US07297591B2

公开(公告)日：2007-11-20

申请号：US10748308

申请日：2003-12-29

申请人： Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

发明人： Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

IPC分类号： H01L21/8242

CPC分类号： H01L21/022 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L28/65

摘要： Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.

摘要翻译： 提供一种半导体器件的电容器。 电容器包括设置在半导体衬底上的电容器下电极。 包含氧化铝（Al 2 O 3 3）的第一电介质层设置在电容器下电极上。 包括具有比氧化铝介电常数更高的介电常数的材料的第二电介质层设置在第一电介质层上。 包含氧化铝的第三电介质层设置在第二电介质层上。 电容器上电极设置在第三电介质层上。 本发明的电容器可以改善电气性能。 因此，可以降低功耗，并且每单位面积的电容足够高以实现高集成度。

公开(公告)号：US07294546B2

公开(公告)日：2007-11-13

申请号：US11519615

申请日：2006-09-12

申请人： Hong-Ki Kim ,  Ho-Kyu Kang ,  Moon-Han Park ,  Myong-Geun Yoon ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Kyung-Hun Kim

发明人： Hong-Ki Kim ,  Ho-Kyu Kang ,  Moon-Han Park ,  Myong-Geun Yoon ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Kyung-Hun Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/10852 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.

摘要翻译： 电容器包括通过物理气相沉积和化学气相沉积形成的上电极。 电容器的上电极可以包括通过化学气相沉积形成的第一上电极和通过物理气相沉积形成的第二上电极。 或者，上电极可以包括通过物理气相沉积形成的第一上电极和通过化学气相沉积形成的第二上电极。 电容器的上电极通过使用化学气相沉积和物理气相沉积的两个步骤形成。 因此，可以使上部电极厚而快速地形成，从而不会劣化上部电极的电特性。

公开(公告)号：US07288453B2

公开(公告)日：2007-10-30

申请号：US11063942

申请日：2005-02-23

申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon

发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon

IPC分类号： H01L21/8234

CPC分类号： H01L28/40 ,  H01L21/02183 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/3211

摘要： There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric layer is formed on the bottom electrode. Then, the capacitor dielectric layer is post-treated in a deoxidizing medium. Then, the post-treated capacitor dielectric layer is post-treated in an oxidizing medium. A top electrode is formed on the post-treated capacitor dielectric layer. The analog capacitor fabricated through the post-treatment as above has a low VCC.

摘要翻译： 提供了使用后处理技术制造模拟电容器的方法。 该方法包括在半导体衬底上形成下绝缘层。 底电极形成在下绝缘层上，电容器电介质层形成在底电极上。 然后，将电容器电介质层在脱氧介质中进行后处理。 然后，将后处理电容器电介质层在氧化介质中进行后处理。 顶部电极形成在后处理电容器介电层上。 通过如上所述的后处理制造的模拟电容具有低VCC。

公开(公告)号：US07166541B2

公开(公告)日：2007-01-23

申请号：US11149498

申请日：2005-06-09

申请人： Min-Woo Song ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Min-Woo Song ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L21/31

CPC分类号： H01L21/02274 ,  C23C16/405 ,  C23C16/45542 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

摘要： A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the reaction chamber; stopping the supply of the source gas and purging the source gas remaining inside the reaction chamber; and supplying oxygen gas into the reaction chamber after purging the source gas, and applying RF power for oxygen plasma treatment, a level of the applied RF power and a partial pressure of the oxygen gas being increased concurrently with an increased aspect ratio of the three-dimensional structure.

摘要翻译： 使用等离子体增强原子层沉积技术形成电介质层的方法包括：将具有三维结构的半导体衬底加载到反应室中; 并重复执行以下步骤，直到形成具有所需厚度的电介质层：将源气体供应到反应室中; 停止源气体的供给并清除剩余在反应室内的源气体; 并且在净化源气体之后将氧气供应到反应室中，并施加用于氧等离子体处理的RF功率，所施加的RF功率的水平和氧气的分压同时增加， 尺寸结构。

公开(公告)号：US20060234466A1

公开(公告)日：2006-10-19

申请号：US11452828

申请日：2006-06-14

申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L21/31637 ,  H01L21/31645

摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

摘要翻译： 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

公开(公告)号：US07091548B2

公开(公告)日：2006-08-15

申请号：US10874461

申请日：2004-06-23

申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC分类号： H01L29/00

CPC分类号： H01L28/40 ,  H01L21/31637 ,  H01L21/31645

摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

摘要翻译： 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

公开(公告)号：US20060163640A1

公开(公告)日：2006-07-27

申请号：US11339151

申请日：2006-01-25

申请人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

发明人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

IPC分类号： H01L29/94

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresponding to a capacitor cell, on each of the lower electrodes to provide a plurality of MIM capacitor cells constituting one capacitor to which the same electric signal is applied.

摘要翻译： 在制造根据该方法制造的金属 - 绝缘体 - 金属（MIM）电容器和金属 - 绝缘体 - 金属（MIM））电容器的方法中，所述方法包括：在半导体衬底上形成绝缘层图案， 层图案具有分别限定要形成电容器单元的区域的多个开口; 在绝缘层图案和半导体衬底上形成下电极导电层; 形成填充所述下电极导电层上的开口的第一牺牲层; 在所述第一牺牲层上形成第二牺牲层; 平面化第二牺牲层; 暴露下电极导电层的上表面; 去除暴露的下电极导电层以形成彼此分离的多个下电极，每个相应于电容器单元; 并且在每个下电极上形成各自对应于电容器单元的电介质层和上电极，以提供构成相同电信号的一个电容器的多个MIM电容器单元。