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    Method of forming a carbon nano-material layer using a cyclic deposition technique
    1.
    发明授权
    Method of forming a carbon nano-material layer using a cyclic deposition technique 有权
    使用循环沉积技术形成碳纳米材料层的方法

    公开(公告)号：US07833580B2

    公开(公告)日：2010-11-16

    申请号：US10859166

    申请日：2004-06-03

    申请人： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

    发明人： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

    IPC分类号： C23C18/00 ,  C23C16/26

    CPC分类号： C23C16/4554 ,  C23C16/0281 ,  C23C16/26 ,  C30B29/02 ,  C30B29/605

    摘要： A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.

    摘要翻译： 形成碳纳米材料层的方法可以包括循环沉积技术。 在该方法中，可以在基板上形成化学吸附层或化学气相沉积层。 杂质可以从化学吸附层或化学气相沉积层去除，以在基底上形成碳原子层。 可以通过重复该方法形成多于一个的碳原子层。

    Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same
    2.
    发明授权
    Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same 有权
    在互连层之间具有垂直延伸的金属 - 绝缘体 - 金属电容器的逻辑器件及其制造方法

    公开(公告)号：US07476922B2

    公开(公告)日：2009-01-13

    申请号：US10969098

    申请日：2004-10-20

    申请人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

    发明人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L28/91 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/0805

    摘要： A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

    摘要翻译： 在互连层之间具有垂直延伸的MIM电容器的逻辑器件包括半导体衬底。 下部互连层位于半导体衬底上方，并且上互连层位于下互连层上。 U形下金属板插入在下互连层和上互连层之间。 U形下金属板直接接触下互连层。 电容器电介质层覆盖下金属板的内表面。 此外，电容器介电层具有插入在下金属板的边缘和上互连层之间的延伸部分。 上金属板覆盖电容器介电层的内表面。 上金属板与上互连层接触并被电容器电介质层约束。

    Method of fabricating analog capacitor using post-treatment technique
    5.
    发明申请
    Method of fabricating analog capacitor using post-treatment technique 有权
    使用后处理技术制造模拟电容的方法

    公开(公告)号：US20050196915A1

    公开(公告)日：2005-09-08

    申请号：US11063942

    申请日：2005-02-23

    申请人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon

    发明人： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon

    IPC分类号： H01L27/10 ,  H01L21/00 ,  H01L21/20 ,  H01L21/8234

    CPC分类号： H01L28/40 ,  H01L21/02183 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/3211

    摘要： There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric layer is formed on the bottom electrode. Then, the capacitor dielectric layer is post-treated in a deoxidizing medium. Then, the post-treated capacitor dielectric layer is post-treated in an oxidizing medium. A top electrode is formed on the post-treated capacitor dielectric layer. The analog capacitor fabricated through the post-treatment as above has a low VCC.

    摘要翻译： 提供了使用后处理技术制造模拟电容器的方法。 该方法包括在半导体衬底上形成下绝缘层。 底电极形成在下绝缘层上，电容器电介质层形成在底电极上。 然后，将电容器电介质层在脱氧介质中进行后处理。 然后，将后处理电容器电介质层在氧化介质中进行后处理。 顶部电极形成在后处理电容器介电层上。 通过如上所述的后处理制造的模拟电容具有低VCC。

    Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same
    6.
    发明申请
    Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same 有权
    在互连层之间具有垂直延伸的金属 - 绝缘体 - 金属电容器的逻辑器件及其制造方法

    公开(公告)号：US20050087879A1

    公开(公告)日：2005-04-28

    申请号：US10969098

    申请日：2004-10-20

    申请人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

    发明人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

    IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/768 ,  H01L23/48 ,  H01L27/08

    CPC分类号： H01L28/91 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/0805

    摘要： A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

    摘要翻译： 在互连层之间具有垂直延伸的MIM电容器的逻辑器件包括半导体衬底。 下部互连层位于半导体衬底上方，并且上互连层位于下互连层上。 U形下金属板插入在下互连层和上互连层之间。 U形下金属板直接接触下互连层。 电容器电介质层覆盖下金属板的内表面。 此外，电容器介电层具有插入在下金属板的边缘和上互连层之间的延伸部分。 上金属板覆盖电容器介电层的内表面。 上金属板与上互连层接触并被电容器电介质层约束。

    Capacitor of semiconductor device and method for manufacturing the same
    8.
    发明申请
    Capacitor of semiconductor device and method for manufacturing the same 审中-公开
    半导体器件的电容器及其制造方法

    公开(公告)号：US20060124987A1

    公开(公告)日：2006-06-15

    申请号：US11345776

    申请日：2006-02-01

    申请人： Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

    发明人： Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

    IPC分类号： H01L29/94

    CPC分类号： H01L21/022 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L28/65

    摘要： Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.

    摘要翻译： 提供一种半导体器件的电容器。 电容器包括设置在半导体衬底上的电容器下电极。 包含氧化铝（Al 2 O 3 3）的第一电介质层设置在电容器下电极上。 包括具有比氧化铝介电常数更高的介电常数的材料的第二电介质层设置在第一电介质层上。 包含氧化铝的第三电介质层设置在第二电介质层上。 电容器上电极设置在第三电介质层上。 本发明的电容器可以改善电气性能。 因此，可以降低功耗，并且每单位面积的电容足够高以实现高集成度。