公开(公告)号：US06245611B1

公开(公告)日：2001-06-12

申请号：US09434385

申请日：1999-11-05

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： H01L218244

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

公开(公告)号：US5447268A

公开(公告)日：1995-09-05

申请号：US244535

申请日：1994-08-25

申请人： Masashi Fukui ,  Atsushi Shimura ,  Takayoshi Sakamoto ,  Yutaka Hoshino

发明人： Masashi Fukui ,  Atsushi Shimura ,  Takayoshi Sakamoto ,  Yutaka Hoshino

IPC分类号： H01R39/32 ,  H02K13/04 ,  H01R43/06

CPC分类号： H02K13/04 ,  H01R39/32 ,  Y10T29/49011

摘要： A method which permits easy fusion of commutator risers to armature coils of an electric motor. When there are 20 risers, for example, 10 through-holes are formed in the boss portion of the armature core of the motor, each through-hole being so sized that the back surfaces of two adjacent risers are exposed through each through-hole. Sub-electrodes are inserted into the through-holes such that each sub-electrode supports the back side of the two risers exposed through the through-hole which receives this sub-electrode. First and second main electrodes are so arranged that the first electrode contacts with the first riser of the first riser group exposed through the first through-hole while the second main electrode contacts the second riser of the sixth riser group exposed through the sixth through-hole. After conducting fusing on these risers, the main electrodes are shifted into contact with the risers which are the second as counted from the risers which have just been fused, and fusion is conducted on these risers. This operation is repeated until all the risers are fused.

摘要翻译： PCT No.PCT / JP93 / 01411 Sec。 371日期：1994年8月25日 102（e）日期1994年8月25日PCT提交1993年10月1日PCT公布。 第WO94 / 09550号公报 日期1994年04月28日。一种允许换向器立管容易地融合到电动机的电枢线圈的方法。 当存在20个立管时，例如，在电动机的电枢铁心的凸起部分中形成10个通孔，每个通孔的尺寸使得两个相邻立管的背面通过每个通孔露出。 子电极插入到通孔中，使得每个子电极支撑通过接收该子电极的通孔暴露的两个提升管的背面。 第一和第二主电极被布置成使得第一电极与通过第一通孔暴露的第一提升管组的第一提升管接触，而第二主电极接触通过第六通孔暴露的第六提升管组的第二提升管 。 在这些立管上进行融合之后，主电极与刚刚融合的立管计数的第二个升降器接触，并且在这些立管上进行融合。 重复此操作直到所有立管融合。

公开(公告)号：US20120235250A1

公开(公告)日：2012-09-20

申请号：US13486153

申请日：2012-06-01

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

摘要翻译： 在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。 连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

公开(公告)号：US20120228711A1

公开(公告)日：2012-09-13

申请号：US13409728

申请日：2012-03-01

申请人： Yutaka HOSHINO

发明人： Yutaka HOSHINO

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10894 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7833

摘要： A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region . It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer , step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region , step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region.

摘要翻译： 半导体器件在薄膜区域中具有第一元件区域，第二元件区域和第一隔离区域，并且在厚膜区域中具有第三元件区域，第四元件区域和第二隔离区域。 制造步骤（a），提供具有通过绝缘层形成的硅层的衬底，步骤（b）在第一隔离区域中的硅层和衬底步骤的第二隔离区域中形成元件隔离绝缘膜 （c）在所述薄膜区域中形成硬掩模，在从所述第三元件区域和所述第四元件区域中的所述硬掩模露出的所述硅层上形成硅膜的步骤（d），以及形成元件的步骤（e） 在第三元件区域中的硅膜和第四元件区域之间的隔离绝缘膜。

公开(公告)号：US08232595B2

公开(公告)日：2012-07-31

申请号：US13111001

申请日：2011-05-19

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/74

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

摘要翻译： 在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。 连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

公开(公告)号：US08134408B2

公开(公告)日：2012-03-13

申请号：US12617488

申请日：2009-11-12

申请人： Tsuyoshi Kawakami ,  Akihiko Furukawa ,  Satoshi Yamakawa ,  Tetsuya Iida ,  Masao Kondo ,  Yutaka Hoshino

发明人： Tsuyoshi Kawakami ,  Akihiko Furukawa ,  Satoshi Yamakawa ,  Tetsuya Iida ,  Masao Kondo ,  Yutaka Hoshino

IPC分类号： H03F3/26

CPC分类号： H03F3/211 ,  H03F1/56 ,  H03F3/26 ,  H03F2200/537 ,  H03F2203/21139

摘要： In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

摘要翻译： 为了实现功率放大电路的频率特性的更宽的带宽，通过二次电感器将分别以不同频率匹配的差分推挽放大器的输出组合在一起，并且输出组合信号。

公开(公告)号：US07994567B2

公开(公告)日：2011-08-09

申请号：US12823453

申请日：2010-06-25

申请人： Tomoyuki Miyake ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Makoto Hatori

发明人： Tomoyuki Miyake ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Makoto Hatori

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66659 ,  H01L21/823425 ,  H01L23/3677 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/7835 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n− type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.

摘要翻译： 为了减小尺寸并提高具有由硅功率MOSFET组成的放大器元件的RF功率模块的功率附加效率，通常形成权衡关系的导通电阻和反馈电容通过形成结构 存在于功率MOSFET的栅极电极和n +型漏极区域之间的偏移漏极区域，成为双偏移漏极区域。 更具体地说，这是通过将最接近栅电极的n型偏移漏极区域的杂质浓度调整为相对较低而调整n型偏移漏极区域的杂质浓度来实现的，该杂质浓度远离 栅电极，要比较高。

公开(公告)号：US07982263B2

公开(公告)日：2011-07-19

申请号：US12609323

申请日：2009-10-30

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/10 ,  H01L29/739 ,  H01L29/74

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

摘要翻译： 在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。 连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

公开(公告)号：US07741656B2

公开(公告)日：2010-06-22

申请号：US12644968

申请日：2009-12-22

申请人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

发明人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC分类号： H01L29/76

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

摘要： A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

公开(公告)号：US20100097156A1

公开(公告)日：2010-04-22

申请号：US12644968

申请日：2009-12-22

申请人： Fumitaka NAKAYAMA ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

发明人： Fumitaka NAKAYAMA ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC分类号： H03H7/38 ,  H01L27/06 ,  H03H2/00

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

摘要： A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.