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公开(公告)号：US09620081B2
公开(公告)日：2017-04-11
申请号：US14477454
申请日：2014-09-04
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Peter F. Holland , Marc Albrecht , Christopher P. Tann
CPC classification number: G09G5/10 , G09G3/2044 , G09G3/3406 , G09G5/12 , G09G5/36 , G09G2320/0646 , G09G2330/021 , G09G2340/10 , G09G2360/144 , G09G2370/04
Abstract: Systems, apparatuses, and methods for synchronizing backlight adjustments to frame updates in a display pipeline. A change in the ambient light is detected and as a result, backlight settings are adjusted. To offset a reduction in the backlight, the color intensity in the frames is increased. While the change in ambient light is detected asynchronously, the adjustment to the backlight settings and color intensity is synchronized to a frame update via a virtual channel for the auxiliary channel of the display interface.
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52.发明申请公开(公告)号：US20160300546A1
公开(公告)日：2016-10-13
申请号：US14855733
申请日：2015-09-16
Applicant: Apple Inc.
Inventor： Fenghua Zheng , Christopher P. Tann , David S. Zalatimo , James E. C. Brown , Sandro H. Pintz
IPC: G09G5/00
CPC classification number: G09G3/2096 , G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , G09G2310/06 , G09G2310/08 , G09G2330/021
Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.
Abstract translation: 显示器可以具有由显示驱动器电路控制的像素阵列。 栅极驱动器电路将栅极线信号提供给像素的行。 栅极驱动器电路可以包括栅极驱动器集成电路。 每个栅极驱动器集成电路可以具有将栅极线信号提供给像素行的移位寄存器。 显示驱动器电路将时钟信号提供给栅极驱动器集成电路。 每个栅极驱动器集成电路可以具有选择性地使能和禁止的一个或多个时钟树。 每个栅极驱动器集成电路可以具有由来自控制器的控制信号控制的控制器和缓冲器。 可以调整缓冲器以提供或不向该栅极驱动器集成电路中的相关联的时钟树提供时钟信号。
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公开(公告)号：US20160277706A1
公开(公告)日：2016-09-22
申请号：US14659723
申请日：2015-03-17
Applicant: APPLE INC.
Inventor： Christopher P. Tann , Chaohao Wang , David S. Zalatimo , Marc Albrecht , Paolo Sacchetto , Sandro H. Pintz , Satish S. Iyengar
CPC classification number: H04N7/0127 , G06F1/3218 , G06F1/3265 , G09G5/001 , G09G2330/021 , H04N7/0115 , Y02D10/153
Abstract: Systems and methods for controlling operation of an electronic display are provided. One embodiment describes an electronic display, which includes a display driver that writes image frames to pixels of the electronic display with a first refresh rate or a second refresh rate; and a timing controller that receives a plurality of image frames from an image source, in which the plurality of image frames are displayed on the electronic display to play video content; detects a cadence with which the plurality of image frames are received from the image source; and, based at least in part on the cadence of the plurality of image frames, instructs the display driver to write each of the plurality of image frames either as a single image frame at the first refresh rate or an image frame at the first refresh rate followed by a repeat of the image frame at the second refresh rate.
Abstract translation: 提供了一种用于控制电子显示器操作的系统和方法。 一个实施例描述了一种电子显示器，其包括以第一刷新率或第二刷新率将图像帧写入电子显示器的像素的显示驱动器; 以及定时控制器，其从图像源接收多个图像帧，其中所述多个图像帧在所述电子显示器上显示以播放视频内容; 从图像源检测接收到多个图像帧的节奏; 并且至少部分地基于多个图像帧的节奏，指示显示驱动器将多个图像帧中的每一个作为第一刷新率的单个图像帧或以第一刷新率的图像帧进行写入 随后以第二刷新率重复图像帧。
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公开(公告)号：US20160260416A1
公开(公告)日：2016-09-08
申请号：US14636693
申请日：2015-03-03
Applicant: APPLE INC.
Inventor： Christopher P. Tann , David S. Zalatimo , Marc Albrecht , Sandro H. Pintz , Satish S. Iyengar
IPC: G09G5/18
CPC classification number: G09G5/005 , G09G2340/0407 , G09G2340/0435 , H04N7/0127
Abstract: One embodiment of the present disclosure describes an electronic display. The electronic display includes a display driver that write image frames to pixels of the electronic display with a first refresh rate or a second refresh rate, in which the second refresh rate is less than the first refresh rate. Additionally, the electronic display includes a timing controller that receives image frames from an image source, in which one or more of the image frames are configured to be displayed on the display panel to play video content; determines a capture rate of the video content based at least in part on a cadence with which the image frames are received, in which the capture rate describes a rate at which each of the one or more image frames was captured by an image sensor; and instructs the display driver to write the one or more of the image frames at the second refresh when the second refresh rate is an integer multiple of the capture rate.
Abstract translation: 本公开的一个实施例描述了电子显示器。 电子显示器包括显示驱动器，其以第一刷新率或第二刷新率将图像帧写入电子显示器的像素，其中第二刷新率小于第一刷新率。 此外，电子显示器包括定时控制器，其从图像源接收图像帧，其中一个或多个图像帧被配置为在显示面板上显示以播放视频内容; 至少部分地基于接收到图像帧的节奏来确定视频内容的捕获率，其中捕获速率描述一个或多个图像帧中的每一个被图像传感器捕获的速率; 并且当第二刷新率是捕获率的整数倍时，指示显示驱动器在第二次刷新时写入一个或多个图像帧。
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公开(公告)号：US09390690B2
公开(公告)日：2016-07-12
申请号：US14319963
申请日：2014-06-30
Applicant: APPLE INC.
Inventor： Marc Albrecht , Christopher P. Tann
CPC classification number: G09G3/2055 , G09G3/2003 , G09G3/2051 , G09G3/2066 , G09G5/393 , G09G2310/08 , G09G2320/0247 , G09G2320/0266 , G09G2330/021 , G09G2330/022 , G09G2340/0435
Abstract: Systems, methods, and device are provided to perform refresh-rate dependent dithering. One embodiment of the present disclosure describes a computing device that includes an image source that generates spatially dithered image data and an electronic display communicatively coupled to the image source. More specifically, the electronic display receives the spatially dithered image data from the image source and determines a refresh rate with which to display an image by comparing a local histogram and an artifact histogram, in which the local histogram describes pixel grayscale distribution of a portion of the image and the artifact histogram describes a pixel grayscale distribution that when displayed will cause a perceivable artifact. Additionally, when the determined refresh rate is less than a threshold refresh rate of the electronic device, the electronic display spatially dithers the image data without temporally dithering the image data and displays the image based at least in part on the spatially dithered image data.
Abstract translation: 提供系统，方法和设备来执行刷新速率相关的抖动。 本公开的一个实施例描述了一种计算设备，其包括生成空间抖动图像数据的图像源和通信地耦合到图像源的电子显示器。 更具体地，电子显示器从图像源接收空间抖动的图像数据，并且通过比较局部直方图和伪影直方图来确定用于显示图像的刷新率，其中局部直方图描述了一部分的像素灰度分布 图像和伪像直方图描述了像素灰度分布，当显示时会产生可察觉的神器。 此外，当确定的刷新率小于电子设备的阈值刷新率时，电子显示器在空间上抖动图像数据而不会暂时地抖动图像数据，并且至少部分地基于空间抖动的图像数据来显示图像。
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Patent Agency Ranking
公开(公告)号：US20240096263A1
公开(公告)日：2024-03-21
申请号：US18353584
申请日：2023-07-17
Applicant: Apple Inc.
Inventor： Denis M. Darmon , Christopher P. Tann , Hopil Bae , Yanghyo Kim , Ramana V. Rachakonda , Xiaofeng Wang , Robert D. Zucker
CPC classification number: G09G3/2096 , G02B26/0833 , G09G2320/0626 , G09G2330/021 , G09G2360/18
Abstract: A device may include image processing circuitry that generates image data corresponding to an image to be displayed during a first image frame and a second image frame. However, the image data is not regenerated for the second image frame. The device may also include an electronic display having a frame buffer that receives and stores the image data from the image processing circuitry. The electronic display may also include a display panel that displays the image during the first image frame based on a first read of the image data from the frame buffer in response to a first emission sync signal and displays the image during the second image frame based on a second read of the image data from the frame buffer in response to a second emission sync signal.
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公开(公告)号：US20220358895A1
公开(公告)日：2022-11-10
申请号：US17752651
申请日：2022-05-24
Applicant: Apple Inc.
Inventor： Mahesh B. Chappalli , Christopher P. Tann , Peter F. Holland , Guy Côté , Stephan Lachowsky
Abstract: An electronic display pipeline may process image data for display on an electronic display. The electronic display pipeline may include burn-in compensation statistics collection circuitry and burn-in compensation circuitry. The burn-in compensation statistics collection circuitry may collect image statistics based at least in part on the image data. The statistics may estimate a likely amount of non-uniform aging of the sub-pixels of the electronic display. The burn-in compensation circuitry may apply a gain to sub-pixels of the image data to account for non-uniform aging of corresponding sub-pixels of the electronic display. The applied gain may be based at least in part on the image statistics collected by the burn-in compensation statistics collection circuitry.
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公开(公告)号：US10983583B2
公开(公告)日：2021-04-20
申请号：US16110953
申请日：2018-08-23
Applicant: Apple Inc.
Inventor： Peter F. Holland , Christopher P. Tann , Malcolm D. Gray , Hari Ganesh R. Thirunageswaram , Kristan Jon Monsen
IPC: G09G5/36 , G06F1/32 , G06T1/60 , G09G5/00 , G06F1/3234 , G06F1/3296 , G06T15/00 , G06T1/20
Abstract: The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).
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公开(公告)号：US10762820B2
公开(公告)日：2020-09-01
申请号：US16269439
申请日：2019-02-06
Applicant: Apple Inc.
Inventor： Christopher P. Tann , Taesung Kim , Sandro H. Pintz
IPC: G09G3/20
Abstract: System and method for improving displayed image quality of an electronic display that displays a first image frame by applying a first voltage to a display pixel and a second image frame directly before the first image frame by applying a second voltage to the display pixel. A display pipeline is communicatively coupled to the electronic display and receives first image data corresponding with the first image frame, where the image data includes a first grayscale value corresponding with the display pixel. Additionally the display pipeline determines an inversion balancing grayscale offset based at least in part on the first grayscale value when polarity of the first voltage and polarity of the second voltage are the same and determines magnitude of the first voltage by applying the inversion balancing grayscale offset to the first grayscale value to reduce likelihood of a perceivable luminance spike when displaying the first image frame.
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公开(公告)号：US10600379B2
公开(公告)日：2020-03-24
申请号：US16103852
申请日：2018-08-14
Applicant: Apple Inc.
Inventor： Prasanna Nambi , Jason N. Gomez , Fenghua Zheng , Paolo Sacchetto , Sandro H. Pintz , Taesung Kim , Christopher P. Tann , Marc Albrecht , David W. Lum
Abstract: The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.
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