MULTI-FRAME-HISTORY PIXEL DRIVE COMPENSATION

    公开(公告)号:US20210056915A1

    公开(公告)日:2021-02-25

    申请号:US16545975

    申请日:2019-08-20

    Applicant: Apple Inc.

    Abstract: Image data for a current image frame may be compensated for transient response variations due to changes to pixel values from one frame to another over time by performing pixel drive compensation. The pixel drive compensation may be performed using a current pixel value and a historical pixel value. The historical pixel value may be the same as a pixel value in the directly previous frame in some conditions, while in other conditions the historical pixel value may be modified from a previous image frame in light of a prior pixel value occurring before the previous image frame. In this way, drive compensation corresponding to image data of a subsequent image frame may be determined based at least in part on a multi-frame history. Even so, the memory bandwidth and/or power consumed to use a multi-frame history to determine a drive compensation may be reduced.

    Adjustable underrun outputs
    53.
    发明授权

    公开(公告)号:US10789877B2

    公开(公告)日:2020-09-29

    申请号:US16515952

    申请日:2019-07-18

    Applicant: APPLE INC.

    Abstract: Devices and methods for underrun compensation are provided. By way of example, a technique for underrun compensation includes determining a particular one of a plurality of pixel configurations for a display. When an underrun condition is detected during processing of first image data via an image processing pipeline, at least a portion of requested image data for downstream processing has not yet been provided by an upstream processing component. Accordingly, upon detecting an underrun condition, underrun pixel data for the at least portion of the requested image data is generated, based upon the particular one of the plurality of pixel configurations.

    Display pipeline memory bandwidth allocation systems and methods

    公开(公告)号:US10713748B2

    公开(公告)日:2020-07-14

    申请号:US16122473

    申请日:2018-09-05

    Applicant: Apple Inc.

    Abstract: Display pipeline may manage allocation of total memory bandwidth to memory access requester blocks (e.g., display pipeline as a whole and/or a block in the display pipeline) by dynamically allocating the total memory bandwidth based at least in part on a calculated bandwidth floor to reduce the communication inefficiency (e.g., underruns), excessive power consumption, and image quality degradation of the display pipeline. Image fetch parameters, electronic display parameters, display pipeline parameters, and memory access requester block parameters may be used to determine the appropriate bandwidth floor for each memory access requester of the display pipeline. Additional memory bandwidth may be allocated to memory access requesters of the display pipeline when available bandwidth remains to further reduce likelihood of subsequent communication inefficiencies in the display pipeline.

    Systems and methods for inserting intra-frame pause

    公开(公告)号:US10261632B2

    公开(公告)日:2019-04-16

    申请号:US15655560

    申请日:2017-07-20

    Applicant: Apple Inc.

    Abstract: One embodiment describes an electronic display that includes display driver circuitry that displays at least a first image frame and a second image frame on the electronic device using a first display pixel and a second display pixel. A timing controller of the electronic display determines at least a first insertion time for a first intra-frame pause for the first image frame and a second insertion time for a second intra-frame pause for the second image frame, which pause rendering of image data to allow the touch sensing circuitry to detect user interaction. The insertion times for the first and second intra-frame pauses are varied from one another by a determined step size.

    ELECTRONIC DISPLAY COLOR ACCURACY COMPENSATION

    公开(公告)号:US20190080656A1

    公开(公告)日:2019-03-14

    申请号:US15699366

    申请日:2017-09-08

    Applicant: Apple Inc.

    Abstract: Systems, methods, and non-transitory media are presented that provide for improving color accuracy. An electronic display includes a display region having multiple pixels each having multiple subpixels. The electronic device also includes a display pipeline coupled to the electronic display. The display pipeline is configured to receive image data and perform white point compensation on the image data to compensate for a current drop in the display to cause the display to display a target white point when displaying white. The display pipeline also is configured to correct white point overcompensation on the image data to reduce possible oversaturation of non-white pixels using the white point compensation. Finally, the display pipeline is configured to output the compensated and corrected image data to the electronic display to facilitate displaying the compensated and corrected image data on the display region.

    SYSTEM FOR MANAGING MEMORY DEVICES
    60.
    发明申请

    公开(公告)号:US20180032281A1

    公开(公告)日:2018-02-01

    申请号:US15225343

    申请日:2016-08-01

    Applicant: Apple Inc.

    Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

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