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公开(公告)号：US20160020203A1
公开(公告)日：2016-01-21
申请号：US14533187
申请日：2014-11-05
Applicant: Apple Inc.
Inventor： Xin Yi Zhang , Xiaofeng Fan , Junjun Li
CPC classification number: H01L27/0255 , H01L29/785
Abstract: In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.
Abstract translation: 在一个实施例中，提供ESD保护电路，其中可以在绝缘半导体区域内的N +和P +扩散之间形成二极管，并且可以在相邻导电类型的相邻绝缘区域之间形成附加二极管。 二极管可以并联使用以形成ESD保护电路，其可以具有低导通电阻并且可能吸收每单位面积的高ESD电流。 为了支持ESD保护电路的形成，每个硅区域可以具有交替的N +和P +扩散，并且相邻的硅区域可以在相对的位置上交替地具有N +和P +扩散。 这是在一个相邻区域的N +扩散之间绘制的垂线可以在另一相邻区域中相交P +扩散，反之亦然。
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公开(公告)号：US20150270258A1
公开(公告)日：2015-09-24
申请号：US14220293
申请日：2014-03-20
Applicant: Apple Inc.
Inventor： Sanjay Dabral , Xiaofeng Fan , Geertjan Joordens
CPC classification number: H01L27/0285 , H02H3/20 , H02H3/22 , H02H9/046
Abstract: ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event.
Abstract translation: 公开了ESD保护电路。 在一个实施例中，集成电路包括第一和第二传感器电路。 第一传感器电路具有第一电阻 - 电容（RC）时间常数，而第二传感器电路具有第二RC时间常数。 第一传感器电路的RC时间常数比第二传感器电路的RC时间常数至少大一个数量级。 第一钳位晶体管耦合到并被配置为由第一传感器电路激活，响应于后者检测ESD事件。 第二钳位晶体管被耦合到并被配置为由第二传感器电路激活，响应于后者检测ESD事件。
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公开(公告)号：US20150256725A1
公开(公告)日：2015-09-10
申请号：US14202256
申请日：2014-03-10
Applicant: Apple Inc.
Inventor： Tongbi T. Jiang , Xiaofeng Fan
CPC classification number: H04N5/2253 , H01L2224/16225 , H01L2224/27013 , H01L2924/10157 , H01L2924/15151 , H04N5/2257 , H04N5/374
Abstract: A CMOS imager assembly may include an integrated circuit (IC) having an active-pixel image sensor that is mounted on a printed circuit board (PCB) substrate using flip chip packaging technology. The IC and the PCB may be physically and electrically connected to each other through multiple electrically conductive connectors. An underfill material (which may include an anti-reflective material) may, during assembly, be introduced around the connectors in the space between the IC and the PCB. A chemical or physical discontinuity on the integrated circuit may, during assembly, prevent the underfill material from entering an area framed by the discontinuity, which may include the pixel array of the image sensor. The discontinuity may include a dam-like structure built up on the IC, a trench-like structure created on the IC, or a low surface tension material that has been applied to the surface of the IC.
Abstract translation: CMOS成像器组件可以包括具有使用倒装芯片封装技术安装在印刷电路板（PCB）衬底上的有源像素图像传感器的集成电路（IC）。 IC和PCB可以通过多个导电连接器物理和电连接。 在组装期间，底部填充材料（其可以包括抗反射材料）可以在IC和PCB之间的空间中的连接器周围引入。 在组装期间，集成电路上的化学或物理不连续性可以在组装期间防止底部填充材料进入由不连续构成的区域，其可以包括图像传感器的像素阵列。 不连续性可以包括在IC上构建的坝状结构，在IC上形成的沟槽状结构或已经施加到IC的表面的低表面张力材料。
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公开(公告)号：US20140320718A1
公开(公告)日：2014-10-30
申请号：US14324179
申请日：2014-07-05
Applicant: Apple Inc.
Inventor： Xiaofeng Fan
IPC: H01L27/146
CPC classification number: H04N5/369 , H01L27/14614 , H01L27/14616 , H01L27/14634 , H01L27/14638 , H01L27/1464 , H01L27/14641 , H01L27/14643 , H01L27/14654 , H01L27/14843 , H01L29/7827 , H04N5/335 , H04N9/045
Abstract: A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.
Abstract translation: 具有光电二极管芯片和晶体管阵列芯片的垂直堆叠图像传感器。 光电二极管芯片包括至少一个光电二极管，并且传输门从光电二极管芯片的顶表面垂直延伸。 图像传感器还包括堆叠在光电二极管芯片顶部的晶体管阵列芯片。 晶体管阵列芯片包括控制电路和存储节点。 图像传感器还包括垂直堆叠在晶体管阵列芯片上的逻辑芯片。 传输门将数据从至少一个光电二极管传送到晶体管阵列芯片，逻辑芯片选择性地激活垂直传输门，复位栅极，源极跟随器栅极和行选择栅极。
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公开(公告)号：US08773562B1
公开(公告)日：2014-07-08
申请号：US13756459
申请日：2013-01-31
Applicant: Apple Inc.
Inventor： Xiaofeng Fan
CPC classification number: H04N5/369 , H01L27/14614 , H01L27/14616 , H01L27/14634 , H01L27/14638 , H01L27/1464 , H01L27/14641 , H01L27/14643 , H01L27/14654 , H01L27/14843 , H01L29/7827 , H04N5/335 , H04N9/045
Abstract: A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.
Abstract translation: 具有光电二极管芯片和晶体管阵列芯片的垂直堆叠图像传感器。 光电二极管芯片包括至少一个光电二极管，并且传输门从光电二极管芯片的顶表面垂直延伸。 图像传感器还包括堆叠在光电二极管芯片顶部的晶体管阵列芯片。 晶体管阵列芯片包括控制电路和存储节点。 图像传感器还包括垂直堆叠在晶体管阵列芯片上的逻辑芯片。 传输门将数据从至少一个光电二极管传送到晶体管阵列芯片，逻辑芯片选择性地激活垂直传输门，复位栅极，源极跟随器栅极和行选择栅极。
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Patent Agency Ranking
公开(公告)号：US20240079440A1
公开(公告)日：2024-03-07
申请号：US17903067
申请日：2022-09-06
Applicant: Apple Inc.
Inventor： Oray O. Cellek , Fei Tan , Gershon Rosenblum , Hong Wei Lee , Cheng-Ying Tsai , Jae Y. Park , Christophe Verove , John L Orlowski , Siddharth Joshi , Xiangli Li , David Coulon , Xiaofeng Fan , Keith Lyon , Nicolas Hotellier , Arnaud Laflaquière
IPC: H01L27/146 , H04N5/378
CPC classification number: H01L27/14652 , H01L27/14621 , H01L27/14636 , H01L27/1465 , H04N5/378
Abstract: A multispectral sensing device includes a first die, including silicon, which is patterned to define a first array of sensor elements, which output first electrical signals in response to optical radiation that is incident on the device in a band of wavelengths less than 1000 nm that is incident on the front side of the first die. A second die has its first side bonded to the back side of the first die and includes a photosensitive material and is patterned to define a second array of sensor elements, which output second electrical signals in response to the optical radiation that is incident on the device in a second band of wavelengths greater than 1000 nm that passes through the first die and is incident on the first side of the second die. Readout circuitry reads the first electrical signals and the second electrical signals serially out of the device.
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公开(公告)号：US10951008B2
公开(公告)日：2021-03-16
申请号：US16867594
申请日：2020-05-06
Applicant: APPLE INC.
Inventor： Chin Han Lin , Weiping Li , Xiaofeng Fan
Abstract: An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.
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公开(公告)号：US20200286946A1
公开(公告)日：2020-09-10
申请号：US16876511
申请日：2020-05-18
Applicant: Apple Inc.
Inventor： Shingo Mandai , Cristiano L. Niclass , Nobuhiro Karasawa , Xiaofeng Fan , Arnaud Laflaquiere , Gennadiy A. Agranov
IPC: H01L27/146 , G01S7/4863 , H04N5/355 , H04N5/357 , H04N5/3745 , H04N5/376 , H04N5/378 , H01L31/107 , H04N5/369
Abstract: A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions.
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公开(公告)号：US20190356112A1
公开(公告)日：2019-11-21
申请号：US16524313
申请日：2019-07-29
Applicant: APPLE INC.
Inventor： Chin Han Lin , Weiping Li , Xiaofeng Fan
Abstract: An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.
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公开(公告)号：US10411437B2
公开(公告)日：2019-09-10
申请号：US16180041
申请日：2018-11-05
Applicant: APPLE INC.
Inventor： Chin Han Lin , Weiping Li , Xiaofeng Fan
Abstract: An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.
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