公开(公告)号：US20200019406A1

公开(公告)日：2020-01-16

申请号：US16034844

申请日：2018-07-13

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Jagadish B. Kotra

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897

Abstract: Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.

公开(公告)号：US10379944B2

公开(公告)日：2019-08-13

申请号：US15489438

申请日：2017-04-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Shrikanth Ganapathy ,  Steven Raasch

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/42 ,  H03M13/19

Abstract: A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.

公开(公告)号：US20180024837A1

公开(公告)日：2018-01-25

申请号：US15216094

申请日：2016-07-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski ,  John Kalamatianos ,  Shomit N. Das

IPC: G06F9/38 ,  G06F9/30

Abstract: An asynchronous pipeline includes a first stage and one or more second stages. A controller provides control signals to the first stage to indicate a modification to an operating speed of the first stage. The modification is determined based on a comparison of a completion status of the first stage to one or more completion statuses of the one or more second stages. In some cases, the controller provides control signals indicating modifications to an operating voltage applied to the first stage and a drive strength of a buffer in the first stage. Modules can be used to determine the completion statuses of the first stage and the one or more second stages based on the monitored output signals generated by the stages, output signals from replica critical paths associated with the stages, or a lookup table that indicates estimated completion times.

公开(公告)号：US09424195B2

公开(公告)日：2016-08-23

申请号：US14253785

申请日：2014-04-15

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Johnsy Kanjirapallil John ,  Phillip E. Nevius ,  Robert G. Gelinas

IPC: G11C29/44 ,  G06F12/08 ,  G06F12/12 ,  G06F11/10 ,  G11C15/00 ,  G11C29/04

CPC classification number: G06F12/0864 ,  G06F11/1064 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0873 ,  G06F12/0888 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/28 ,  G06F2212/283 ,  G06F2212/284 ,  G06F2212/403 ,  G11C15/00 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/0409

Abstract: A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index.

Abstract translation: 一种管理高速缓存存储器的方法包括以对应于在访问请求中指定的地址的主要索引访问高速缓冲存储器。 确定在主索引处访问高速缓冲存储器不会导致在具有无错状态的高速缓存行上的高速缓存命中。 响应于该确定，主索引被映射到次索引，并且该地址的数据被写入到次级索引处的高速缓存行。

公开(公告)号：US20150026414A1

公开(公告)日：2015-01-22

申请号：US13944148

申请日：2013-07-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Paul Keltcher ,  Marius Evers ,  Chitresh Narasimhaiah

IPC: G06F12/08

Abstract: A prefetcher maintains the state of stored prefetch information, such as a prefetch confidence level, when a prefetch would cross a memory page boundary. The maintained prefetch information can be used both to identify whether the stride pattern for a particular sequence of demand requests persists after the memory page boundary has been crossed, and to continue to issue prefetch requests according to the identified pattern. The prefetcher therefore does not have re-identify a stride pattern each time a page boundary is crossed by a sequence of demand requests, thereby improving the efficiency and accuracy of the prefetcher.

Abstract translation: 当预取将跨越内存页边界时，预取器维护存储的预取信息的状态，例如预取置信水平。 可以使用维护的预取信息来识别在存储器页边界已经被越过之后特定的请求请求序列的步幅模式是否持续，并且根据所识别的模式继续发出预取请求。 因此，每次通过一系列请求请求来划分页边界时，预取器不会重新识别步幅，从而提高预取器的效率和准确性。

公开(公告)号：US20130227321A1

公开(公告)日：2013-08-29

申请号：US13854616

申请日：2013-04-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Branover ,  Norman M. Hack ,  Maurice B. Steinman ,  John Kalamatianos ,  Jonathan M. Owen

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

Abstract translation: 公开了一种用于动态控制高速缓存大小的方法和装置。 在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。 该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

公开(公告)号：US12175073B2

公开(公告)日：2024-12-24

申请号：US17139496

申请日：2020-12-31

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Varun Agrawal ,  Niti Madan

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods for reusing remote registers in processing in memory (PIM) are disclosed. A system includes at least a host processor, a memory controller, and a PIM device. When the memory controller receives, from the host processor, an operation targeting the PIM device, the memory controller determines whether an optimization can be applied to the operation. The memory controller converts the operation into N PIM commands if the optimization is not applicable. Otherwise, the memory controller converts the operation into a N−1 PIM commands if the optimization is applicable. For example, if the operation involves reusing a constant value, a copy command can be omitted, resulting in memory bandwidth reduction and power consumption savings. In one scenario, the memory controller includes a constant-value cache, and the memory controller performs a lookup of the constant-value cache to determine if the optimization is applicable for a given operation.

公开(公告)号：US12073251B2

公开(公告)日：2024-08-27

申请号：US17136767

申请日：2020-12-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nagadastagiri Reddy Challapalle ,  Jagadish B. Kotra ,  John Kalamatianos

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: Offloading computations from a processor to remote execution logic is disclosed. Offload instructions for remote execution on a remote device are dispatched in the form of processor instructions like conventional instructions. In the processor, an offload instruction is inserted in an offload queue. The offload instruction may be inserted at the dispatch stage or the retire stage of the processor pipeline. Metadata for the offload instruction is added to the offload instruction in the offload queue. After retirement of the offload instruction, the processor transmits an offload request generated from the offload instruction.

公开(公告)号：US12066950B2

公开(公告)日：2024-08-20

申请号：US17561454

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Niti Madan ,  John Kalamatianos

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F12/0207 ,  G06F12/0882

Abstract: An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria. The memory controller maintains and uses a page table to properly configure memory elements, such as banks in a memory module, for the next memory command, whether a PIM command or a non-PIM command. The page table tracks the status of memory elements as of the most recent memory command that was issued. The page table includes an “All Bank” entry that indicates the status of banks after processing the most recent PIM command. For example, the All Banks entry indicates whether all the banks have a row open and if so, specifies the open row for all the banks.

公开(公告)号：US12026401B2

公开(公告)日：2024-07-02

申请号：US17855109

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Niti Madan ,  Yasuko Eckert ,  Varun Agrawal ,  John Kalamatianos

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second command is issued to open the additional row after the row is last accessed by the instruction.