公开(公告)号：US07825025B2

公开(公告)日：2010-11-02

申请号：US10959674

申请日：2004-10-04

Applicant: Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

Inventor： Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

IPC: H01L21/44 ,  H01L21/477

CPC classification number: H01L21/28518 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/78

Abstract: According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

Abstract translation: 根据本发明的一个实施例，一种用于镍硅化的方法包括提供具有源极区，栅极区和漏极区的衬底，在源区中形成源极和在漏极区中形成漏极，退火源和 漏极，在源极和漏极退火之后注入源区域和漏极区域中的重离子，在源极和漏极区域中的每一个中沉积镍层，并加热衬底以形成硅化镍区域 每个源极和漏极区域通过加热衬底。

公开(公告)号：US20100261298A1

公开(公告)日：2010-10-14

申请号：US12757704

申请日：2010-04-09

Applicant: Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

Inventor： Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

IPC: H01L21/26 ,  H01L21/66

CPC classification number: H01L21/26506 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02667 ,  H01L22/12 ,  H01L22/20

Abstract: A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.

Abstract translation: 一种用于减小具有半导体表面的晶片的曲率的方法。 识别一个或多个工艺步骤，在该处理步骤中，晶片呈现最大的曲率，和/或晶片曲率，其可以降低模具的产量。 晶体损伤过程将半导体表面的至少一部分转化成至少一个非晶表面区域在晶体损坏之后或同时具有晶体损伤的情况下，非晶表面区域通过重结晶退火重结晶，使晶片退火一段时间， 足以使非晶表面区域再结晶的温度。 由于再结晶提供的平均晶片曲率的减小，随后的光刻步骤变得容易。

公开(公告)号：US20090130864A1

公开(公告)日：2009-05-21

申请号：US11942367

申请日：2007-11-19

Applicant: Narendra Singh MEHTA ,  Perry Howard Shields ,  Amitabh Jain

Inventor： Narendra Singh MEHTA ,  Perry Howard Shields ,  Amitabh Jain

IPC: H01L21/02 ,  F27D11/00

CPC classification number: H01L29/78 ,  H01L21/28176 ,  H01L21/324

Abstract: An embodiment generally relates a method of processing semiconductor devices. The method includes forming a semiconductor device and exposing the semiconductor device to a temperature substantially between 1175 to 1375 degrees Celsius after the formation of a gate dielectric layer. The method also includes annealing the semiconductor device for a period of time.

Abstract translation: 实施例通常涉及半导体器件的处理方法。 该方法包括形成半导体器件，并且在形成栅极电介质层之后将半导体器件暴露于基本上在1175至1375摄氏度之间的温度。 该方法还包括半导体器件退火一段时间。

公开(公告)号：US07479668B2

公开(公告)日：2009-01-20

申请号：US11370339

申请日：2006-03-08

Applicant: Amitabh Jain ,  Gordon Pollack

Inventor： Amitabh Jain ,  Gordon Pollack

IPC: H01L31/112

CPC classification number: H01L21/26586 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).

Abstract translation: 本发明在一个实施例中提供一种用于制造金属氧化物半导体（MOS）器件（100）的工艺。 该方法包括在衬底（105）上形成栅极（120）并在衬底（105）中形成源极/漏极延伸部分（160）。 形成源极/漏极延伸部分（160）包括异常倾斜的掺杂剂注入（135）和掺杂剂注入（145）。 异常倾斜的掺杂剂注入（135）使用大于约零度的第一加速能量和倾斜角。 掺杂剂注入（145）使用高于第一加速能量的第二加速能量。 该工艺还包括执行衬底（105）的超高温退火，其中源极/漏极延伸部（160）的部分（170）在栅极（120）下方。

公开(公告)号：US20080318387A1

公开(公告)日：2008-12-25

申请号：US11764980

申请日：2007-06-19

Applicant: Amitabh Jain ,  Manoj Mehrotra

Inventor： Amitabh Jain ,  Manoj Mehrotra

IPC: H01L21/336

CPC classification number: H01L21/2652 ,  H01L21/2255 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/823814 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。 在栅极电介质层上形成栅电极。 将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。 衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

公开(公告)号：US20080268628A1

公开(公告)日：2008-10-30

申请号：US11739965

申请日：2007-04-25

Applicant: Puneet Kohli ,  Manoj Mehrotra ,  Antonio Luis Pacheco Rotondaro ,  Stan Ashburn ,  Nandakumar Mahalingam ,  Amitabh Jain

Inventor： Puneet Kohli ,  Manoj Mehrotra ,  Antonio Luis Pacheco Rotondaro ,  Stan Ashburn ,  Nandakumar Mahalingam ,  Amitabh Jain

IPC: H01L21/425 ,  H01L29/00 ,  H01L21/22

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L29/66575

Abstract: The disclosure relates to a method of forming an n-type doped active area on a semiconductor substrate that presents an improved placement profile. The method comprises the placement of arsenic in the presence of a carbon-containing arsenic diffusion suppressant in order to reduce the diffusion of the arsenic out of the target area during heat-induced annealing. The method may additionally include the placement of an amorphizer, such as germanium, in the target area in order to reduce channeling of the arsenic ions through the crystalline lattice. The method may also include the use of arsenic in addition to another n-type dopant, e.g. phosphorus, in order to offset some of the disadvantages of a pure arsenic dopant. The disclosure also relates to a semiconductor component, e.g. an NMOS transistor, formed in accordance with the described methods.

Abstract translation: 本公开涉及一种在半导体衬底上形成n型掺杂有源区的方法，该方法具有改善的放置曲线。 该方法包括在含碳的砷扩散抑制剂的存在下放置砷，以便在热诱导退火期间减少砷扩散到目标区域之外。 该方法可以另外包括在目标区域中放置诸如锗的非晶硅化合物，以便减少砷离子通过晶格的通道。 该方法还可以包括除了另一种n型掺杂剂之外使用砷，例如， 磷，以便抵消纯砷掺杂剂的一些缺点。 本公开还涉及半导体部件，例如， 一个根据所述方法形成的NMOS晶体管。

公开(公告)号：US20080128837A1

公开(公告)日：2008-06-05

申请号：US12018313

申请日：2008-01-23

Applicant: Peijun J. Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas D. Bonifield ,  Homi Mogul

Inventor： Peijun J. Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas D. Bonifield ,  Homi Mogul

IPC: H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

Abstract translation: 本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。 除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。 该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

公开(公告)号：US07371648B2

公开(公告)日：2008-05-13

申请号：US11469512

申请日：2006-09-01

Applicant: Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

Inventor： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

IPC: H01L21/336 ,  H01L21/04 ,  H01L21/425

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

Abstract: The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

Abstract translation: 本发明提供一种晶体管器件的制造方法及其制造方法。 制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分 所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

公开(公告)号：US07345355B2

公开(公告)日：2008-03-18

申请号：US10942607

申请日：2004-09-15

Applicant: Amitabh Jain ,  Stephanie W. Butler

Inventor： Amitabh Jain ,  Stephanie W. Butler

IPC: H01L29/00 ,  H01L31/0288

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/7833

Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

Abstract translation: 公开了使用多个离子注入步骤在半导体衬底中形成超浅结的方法。 离子注入步骤包括植入至少一种电子活性掺杂剂以及通过在掺杂剂注入期间通过沟槽化和/或通过热扩散来有效地限制结扩展的至少两种物质的注入。 在掺杂剂注入之后，电子活性掺杂剂通过热处理而被激活。

公开(公告)号：US07344929B2

公开(公告)日：2008-03-18

申请号：US11034791

申请日：2005-01-13

Applicant: Manoj Mehrotra ,  Amitabh Jain

Inventor： Manoj Mehrotra ,  Amitabh Jain

IPC: H01L21/00

CPC classification number: H01L21/324 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/7833

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the capping layer (210) having a degree of reflectivity, and annealing the transistor device through the capping layer (210) using photons (310), the annealing of the transistor device affected by the degree of reflectivity.

Abstract translation: 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，制造半导体器件的方法包括在具有位于衬底（110）上方的源/漏区（150,155）的晶体管器件上形成覆盖层（210），所述覆盖层（210）具有 并且通过使用光子（310）的覆盖层（210）退火晶体管器件，晶体管器件的退火受到反射率的影响。