公开(公告)号：US20080268628A1

公开(公告)日：2008-10-30

申请号：US11739965

申请日：2007-04-25

申请人： Puneet Kohli ,  Manoj Mehrotra ,  Antonio Luis Pacheco Rotondaro ,  Stan Ashburn ,  Nandakumar Mahalingam ,  Amitabh Jain

发明人： Puneet Kohli ,  Manoj Mehrotra ,  Antonio Luis Pacheco Rotondaro ,  Stan Ashburn ,  Nandakumar Mahalingam ,  Amitabh Jain

IPC分类号： H01L21/425 ,  H01L29/00 ,  H01L21/22

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L29/66575

摘要： The disclosure relates to a method of forming an n-type doped active area on a semiconductor substrate that presents an improved placement profile. The method comprises the placement of arsenic in the presence of a carbon-containing arsenic diffusion suppressant in order to reduce the diffusion of the arsenic out of the target area during heat-induced annealing. The method may additionally include the placement of an amorphizer, such as germanium, in the target area in order to reduce channeling of the arsenic ions through the crystalline lattice. The method may also include the use of arsenic in addition to another n-type dopant, e.g. phosphorus, in order to offset some of the disadvantages of a pure arsenic dopant. The disclosure also relates to a semiconductor component, e.g. an NMOS transistor, formed in accordance with the described methods.

摘要翻译： 本公开涉及一种在半导体衬底上形成n型掺杂有源区的方法，该方法具有改善的放置曲线。 该方法包括在含碳的砷扩散抑制剂的存在下放置砷，以便在热诱导退火期间减少砷扩散到目标区域之外。 该方法可以另外包括在目标区域中放置诸如锗的非晶硅化合物，以便减少砷离子通过晶格的通道。 该方法还可以包括除了另一种n型掺杂剂之外使用砷，例如， 磷，以便抵消纯砷掺杂剂的一些缺点。 本公开还涉及半导体部件，例如， 一个根据所述方法形成的NMOS晶体管。

公开(公告)号：US20090127620A1

公开(公告)日：2009-05-21

申请号：US11941129

申请日：2007-11-16

申请人： Puneet Kohli ,  Nandakumar Mahalingam ,  Manoj Mehrotra ,  Song Zhao

发明人： Puneet Kohli ,  Nandakumar Mahalingam ,  Manoj Mehrotra ,  Song Zhao

IPC分类号： H01L23/00 ,  H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/7833

摘要： Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance.

摘要翻译： 公开了半导体掺杂技术以及相关方法和结构，其产生具有更紧密控制的源极和漏极延伸区掺杂物分布而不显着引起栅极边缘二极管泄漏的元件。 该技术遵循发现，可以用作掺杂剂如硼的扩散抑制剂的碳可能在源极和漏极延伸区域中以大量存在而产生栅极边缘二极管泄漏。 作为在源极和漏极延伸区域中放置碳的替代方案，可以将碳放置在源极和漏极区域中，并且可以依靠用于激活掺杂剂的热退火将碳的少量浓度扩散到源中， 漏极延伸区域，从而抑制这些区域中的掺杂剂扩散，而不会显着引起栅极边缘二极管泄漏。 源极和漏极区域中增加的碳浓度可能允许源极/漏极区域的较重掺杂，导致改善的栅极电容。

公开(公告)号：US07897496B2

公开(公告)日：2011-03-01

申请号：US11941129

申请日：2007-11-16

申请人： Puneet Kohli ,  Nandakumar Mahalingam ,  Manoj Mehrotra ,  Song Zhao

发明人： Puneet Kohli ,  Nandakumar Mahalingam ,  Manoj Mehrotra ,  Song Zhao

IPC分类号： H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/7833

摘要： Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance.

摘要翻译： 公开了半导体掺杂技术以及相关方法和结构，其产生具有更紧密控制的源极和漏极延伸区掺杂物分布而不显着引起栅极边缘二极管泄漏的元件。 该技术遵循发现，可以用作掺杂剂如硼的扩散抑制剂的碳可能在源极和漏极延伸区域中以大量存在而产生栅极边缘二极管泄漏。 作为在源极和漏极延伸区域中放置碳的替代方案，可以将碳放置在源极和漏极区域中，并且可以依靠用于激活掺杂剂的热退火将碳的少量浓度扩散到源中， 漏极延伸区域，从而抑制这些区域中的掺杂剂扩散，而不会显着引起栅极边缘二极管泄漏。 源极和漏极区域中增加的碳浓度可能允许源极/漏极区域的较重掺杂，导致改善的栅极电容。

公开(公告)号：US20090004803A1

公开(公告)日：2009-01-01

申请号：US11769058

申请日：2007-06-27

申请人： Manoj Mehrotra ,  Stan Ashburn ,  Shaoping Tang

发明人： Manoj Mehrotra ,  Stan Ashburn ,  Shaoping Tang

IPC分类号： G11C11/34 ,  H01L21/8238

CPC分类号： G11C11/412 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/1083 ,  H01L29/7833

摘要： One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.

摘要翻译： 本发明人的概念的一个方面涉及形成半导体器件的方法。 在该方法中，在半导体本体上形成栅极结构。 源极/漏极掩模在半导体本体注入源上形成图案，并且形成与栅极结构相关联的漏极区。 在形成植入的源区和漏区之后，在包括至少两个植入物的源极和漏极区域上执行多级注入，其中第一注入的剂量和能量与第二植入物的剂量和能量不同。 还公开了其它方法和装置。

公开(公告)号：US20080157292A1

公开(公告)日：2008-07-03

申请号：US11703452

申请日：2007-02-07

申请人： Manoj Mehrotra ,  Stan Ashburn

发明人： Manoj Mehrotra ,  Stan Ashburn

IPC分类号： H01L21/31 ,  H01L29/00

CPC分类号： H01L29/7843 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/3143 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/823807 ,  H01L29/66575

摘要： A method for manufacturing a semiconductor device featuring a high-stress dielectric layer is disclosed. The method involves the deposition of a comparatively thick liner layer that exerts increased strain on an underlying gate and active areas, resulting in enhanced carrier mobility through the transistor and heightened transistor performance. The method also involves the amelioration of fabrication problems that might arise from the deposition of a comparatively thick liner layer by forming such layer with at least a partially direction deposition process. Also disclosed are semiconductor devices manufactured in accordance with the disclosed methods.

摘要翻译： 公开了一种制造具有高应力电介质层的半导体器件的方法。 该方法涉及沉积相当厚的衬底层，其在下面的栅极和有源区上施加增加的应变，导致通过晶体管的增强的载流子迁移率和提高的晶体管性能。 该方法还涉及通过用至少部分方向沉积工艺形成这种层来改善可能由沉积较厚的衬层而产生的制造问题。 还公开了根据所公开的方法制造的半导体器件。

公开(公告)号：US07691700B2

公开(公告)日：2010-04-06

申请号：US11769058

申请日：2007-06-27

申请人： Manoj Mehrotra ,  Stan Ashburn ,  Shaoping Tang

发明人： Manoj Mehrotra ,  Stan Ashburn ,  Shaoping Tang

IPC分类号： H01L21/8238

CPC分类号： G11C11/412 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/1083 ,  H01L29/7833

摘要： One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.

摘要翻译： 本发明人的概念的一个方面涉及形成半导体器件的方法。 在该方法中，在半导体本体上形成栅极结构。 源极/漏极掩模在半导体本体注入源上形成图案，并且形成与栅极结构相关联的漏极区。 在形成植入的源区和漏区之后，在包括至少两个植入物的源极和漏极区域上执行多级注入，其中第一注入的剂量和能量与第二植入物的剂量和能量不同。 还公开了其它方法和装置。

公开(公告)号：US20090179280A1

公开(公告)日：2009-07-16

申请号：US11972417

申请日：2008-01-10

申请人： Puneet Kohli ,  Manoj Mehrotra ,  Shaoping Tang

发明人： Puneet Kohli ,  Manoj Mehrotra ,  Shaoping Tang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7833

摘要： Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm−2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed

摘要翻译： n型轻掺杂漏极（NLDD）区域和n型源极/漏极（NDS）区域的管道缺陷与砷植入相关，而NLDD和NSD区域的过度扩散主要是由于磷间质运动。 碳植入通常用于减少NLDD中的磷扩散，但有助于门极二极管泄漏（GDL）。 在高阈值NMOS晶体管中，GDL通常是主要的截止状态泄漏机制。 本发明提供了一种形成NMOS晶体管的方法，其中没有碳注入到NLDD中，并且NSD由前非晶化植入物（PAI），磷植入物和碳种植入物形成。 在NDS中使用碳可以提供更高浓度的磷，从而降低串联电阻并减少管道缺陷。 还公开了在NSD中具有小于1.1014cm-2砷的NMOS晶体管和由本发明方法形成的高阈值NMOS晶体管

公开(公告)号：US20080277730A1

公开(公告)日：2008-11-13

申请号：US11745044

申请日：2007-05-07

申请人： Manoj Mehrotra ,  Antonio L.P Rotondaro ,  Puneet Kohli

发明人： Manoj Mehrotra ,  Antonio L.P Rotondaro ,  Puneet Kohli

IPC分类号： H01L21/44 ,  H01L29/76

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76828 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.

摘要翻译： 提出了形成半导体器件的方法。 该方法包括形成栅极结构，包括在半导体衬底上形成栅电极并在栅电极附近形成间隔物。 在栅极结构附近形成源极/漏极，并且在栅极结构和半导体衬底上形成层压应力层。 层压应力层的形成包括循环沉积工艺以在栅极结构和半导体衬底之上形成第一应力层，并且在第一应力层上形成至少第二应力层。 在层压层形成之后，进行在约900℃以上的温度下进行的退火处理。

公开(公告)号：US20080076227A1

公开(公告)日：2008-03-27

申请号：US11533795

申请日：2006-09-21

申请人： Puneet Kohli ,  Manoj Mehrotra ,  Jin Zhao ,  Sameer Ajmera

发明人： Puneet Kohli ,  Manoj Mehrotra ,  Jin Zhao ,  Sameer Ajmera

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/2686 ,  H01L21/76224 ,  H01L21/76825 ,  H01L29/6659 ,  H01L29/7843

摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes, among other steps, forming a gate structure over a substrate, the gate structure having source/drain regions proximate thereto and in, on or over the substrate, forming a pre-metal dielectric layer over the gate structure and source/drain regions, and subjecting the pre-metal dielectric layer to an energy beam treatment, the energy beam treatment configured to change a stress of the pre-metal dielectric layer, and thus change a stress in the substrate therebelow.

摘要翻译： 本发明提供一种制造半导体器件的方法。 除了其他步骤之外，用于制造半导体器件的方法包括在衬底上形成栅极结构，栅极结构具有靠近其的源极/漏极区域，并且在衬底上，衬底上或上方，在栅极上形成预金属电介质层 结构和源极/漏极区域，并且对金属前介电层进行能量束处理，所述能量束处理被配置为改变预金属介电层的应力，从而改变其下的衬底中的应力。

公开(公告)号：US07736983B2

公开(公告)日：2010-06-15

申请号：US11972417

申请日：2008-01-10

申请人： Puneet Kohli ,  Manoj Mehrotra ,  Shaoping Tang

发明人： Puneet Kohli ,  Manoj Mehrotra ,  Shaoping Tang

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7833

摘要： Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implantation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm−2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed.

摘要翻译： n型轻掺杂漏极（NLDD）区域和n型源极/漏极（NDS）区域的管道缺陷与砷植入相关，而NLDD和NSD区域的过度扩散主要是由于磷间质运动。 碳注入通常用于减少NLDD中的磷扩散，但有助于栅极二极管泄漏（GDL）。 在高阈值NMOS晶体管中，GDL通常是主要的截止状态泄漏机制。 本发明提供了一种形成NMOS晶体管的方法，其中没有碳注入到NLDD中，并且NSD由前非晶化植入物（PAI），磷植入物和碳种植入物形成。 在NDS中使用碳可以提供更高浓度的磷，从而降低串联电阻并减少管道缺陷。 还公开了在NSD中具有小于1×1014cm-2砷的NMOS晶体管和由本发明方法形成的高阈值NMOS晶体管。