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    N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PROFILE AND METHOD OF FORMING SAME
    1.
    发明申请
    N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PROFILE AND METHOD OF FORMING SAME 审中-公开
    具有改进的嫁接轮廓的N型半导体元件及其形成方法

    公开(公告)号：US20080268628A1

    公开(公告)日：2008-10-30

    申请号：US11739965

    申请日：2007-04-25

    申请人： Puneet Kohli ,  Manoj Mehrotra ,  Antonio Luis Pacheco Rotondaro ,  Stan Ashburn ,  Nandakumar Mahalingam ,  Amitabh Jain

    发明人： Puneet Kohli ,  Manoj Mehrotra ,  Antonio Luis Pacheco Rotondaro ,  Stan Ashburn ,  Nandakumar Mahalingam ,  Amitabh Jain

    IPC分类号： H01L21/425 ,  H01L29/00 ,  H01L21/22

    CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L29/66575

    摘要： The disclosure relates to a method of forming an n-type doped active area on a semiconductor substrate that presents an improved placement profile. The method comprises the placement of arsenic in the presence of a carbon-containing arsenic diffusion suppressant in order to reduce the diffusion of the arsenic out of the target area during heat-induced annealing. The method may additionally include the placement of an amorphizer, such as germanium, in the target area in order to reduce channeling of the arsenic ions through the crystalline lattice. The method may also include the use of arsenic in addition to another n-type dopant, e.g. phosphorus, in order to offset some of the disadvantages of a pure arsenic dopant. The disclosure also relates to a semiconductor component, e.g. an NMOS transistor, formed in accordance with the described methods.

    摘要翻译： 本公开涉及一种在半导体衬底上形成n型掺杂有源区的方法，该方法具有改善的放置曲线。 该方法包括在含碳的砷扩散抑制剂的存在下放置砷，以便在热诱导退火期间减少砷扩散到目标区域之外。 该方法可以另外包括在目标区域中放置诸如锗的非晶硅化合物，以便减少砷离子通过晶格的通道。 该方法还可以包括除了另一种n型掺杂剂之外使用砷，例如， 磷，以便抵消纯砷掺杂剂的一些缺点。 本公开还涉及半导体部件，例如， 一个根据所述方法形成的NMOS晶体管。

    Use of indium to define work function of p-type doped polysilicon
    3.
    发明授权
    Use of indium to define work function of p-type doped polysilicon 有权
    使用铟来定义p型掺杂多晶硅的功函数

    公开(公告)号：US07026218B2

    公开(公告)日：2006-04-11

    申请号：US10865342

    申请日：2004-06-10

    申请人： Antonio Luis Pacheco Rotondaro ,  James J. Chambers ,  Amitabh Jain

    发明人： Antonio Luis Pacheco Rotondaro ,  James J. Chambers ,  Amitabh Jain

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/2807

    摘要： The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).

    摘要翻译： 本发明涉及一种PMOS晶体管的形成，其中一层硅或SiGe抑制p型掺杂剂进入下面的栅介质层。 可以将p型掺杂剂添加到覆盖硅或SiGe层的栅电极材料中，并且可以向硅或SiGe层扩散。 硅或SiGe层可以形成为约5至120纳米的厚度，并掺杂有例如铟（In）的掺杂剂，以阻止p型掺杂剂通过硅或SiGe层。 掺杂剂可以在硅或SiGe层的界面附近与硅介电材料的下层之间的硅或SiGe层内具有峰值浓度。 允许栅电极掺杂有p型掺杂剂（例如硼）有助于以具有期望值（例如，与约4.8至约5.6电子伏特的费米能级一致）的相关功函数形成晶体管。

    Use of indium to define work function of p-type doped polysilicon
    4.
    发明授权
    Use of indium to define work function of p-type doped polysilicon 有权

    公开(公告)号：US06803611B2

    公开(公告)日：2004-10-12

    申请号：US10336563

    申请日：2003-01-03

    申请人： Antonio Luis Pacheco Rotondaro ,  James J. Chambers ,  Amitabh Jain

    发明人： Antonio Luis Pacheco Rotondaro ,  James J. Chambers ,  Amitabh Jain

    IPC分类号： H01L2710

    CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/2807

    摘要： The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).

    Semiconductor device made by using a laser anneal to incorporate stress into a channel region
    7.
    发明授权
    Semiconductor device made by using a laser anneal to incorporate stress into a channel region 有权
    通过使用激光退火制造的半导体器件将应力引入沟道区域

    公开(公告)号：US07670917B2

    公开(公告)日：2010-03-02

    申请号：US11853328

    申请日：2007-09-11

    申请人： Amitabh Jain ,  Manoj Mehrotra

    发明人： Amitabh Jain ,  Manoj Mehrotra

    IPC分类号： H01L21/336 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28044 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

    摘要： In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.

    摘要翻译： 在一个方面，提供一种制造半导体器件的方法，包括在半导体衬底上形成栅电极，在栅电极附近形成源极/漏极，在栅电极上沉积应力诱导层。 在至少约1100℃的温度下沉积应力诱导层至少约300微秒的时间之后，至少在栅电极上进行激光退火，并且半导体器件经受热 在进行激光退火之后退火。

    Activation of CMOS source/drain extensions by ultra-high temperature anneals
    8.
    发明授权
    Activation of CMOS source/drain extensions by ultra-high temperature anneals 有权
    通过超高温退火激活CMOS源极/漏极延伸

    公开(公告)号：US07615458B2

    公开(公告)日：2009-11-10

    申请号：US11764980

    申请日：2007-06-19

    申请人： Amitabh Jain ,  Manoj Mehrotra

    发明人： Amitabh Jain ,  Manoj Mehrotra

    IPC分类号： H01L21/331

    CPC分类号： H01L21/2652 ,  H01L21/2255 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/823814 ,  H01L29/6659

    摘要： A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.

    摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。 在栅极电介质层上形成栅电极。 将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。 衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

    Semiconductor Device Made by Using a Laser Anneal to Incorporate Stress into a Channel Region
    9.
    发明申请
    Semiconductor Device Made by Using a Laser Anneal to Incorporate Stress into a Channel Region 有权
    使用激光退火制造的半导体器件将应力引入通道区域

    公开(公告)号：US20090065880A1

    公开(公告)日：2009-03-12

    申请号：US11853328

    申请日：2007-09-11

    申请人： Amitabh Jain ,  Manoj Mehrotra

    发明人： Amitabh Jain ,  Manoj Mehrotra

    IPC分类号： H01L29/94 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28044 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

    摘要： In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.

    摘要翻译： 在一个方面，提供一种制造半导体器件的方法，包括在半导体衬底上形成栅电极，在栅电极附近形成源极/漏极，在栅电极上沉积应力诱导层。 在至少约1100℃的温度下沉积应力诱导层至少约300微秒的时间之后，至少在栅电极上进行激光退火，并且半导体器件经受热 在进行激光退火之后退火。