公开(公告)号：US07119574B1

公开(公告)日：2006-10-10

申请号：US10637258

申请日：2003-08-08

申请人： Andy L Lee ,  Wanli Chang ,  Cameron McClintock ,  John E Turner ,  Brian D Johnson ,  Chiao Kai Hwang ,  Richard Y Chang ,  Richard G Cliff

发明人： Andy L Lee ,  Wanli Chang ,  Cameron McClintock ,  John E Turner ,  Brian D Johnson ,  Chiao Kai Hwang ,  Richard Y Chang ,  Richard G Cliff

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K17/063 ,  H03K19/177 ,  H03K19/1778

摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

摘要翻译： 提出了用于低电压系统的增强型门控结构，其中V 对由单晶闸管通过的信号范围的影响减小。 在一种布置中，通过施加更高的V门极来提高通过NMOS通孔传播的信号的V门极限极限。 在另一种布置中，V 降低。 传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

公开(公告)号：US06879183B2

公开(公告)日：2005-04-12

申请号：US10260712

申请日：2002-09-27

申请人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

发明人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

IPC分类号： H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

摘要翻译： 可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。 每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。 每个逻辑区域包括可编程逻辑的多个子区域。 每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源 装置。

公开(公告)号：US06271679B1

公开(公告)日：2001-08-07

申请号：US09535064

申请日：2000-03-23

申请人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

发明人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

IPC分类号： H03K19177

CPC分类号： H03K19/17744 ,  H03K19/018585

摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

公开(公告)号：US5999016A

公开(公告)日：1999-12-07

申请号：US920298

申请日：1997-08-28

申请人： Cameron McClintock ,  Ninh Ngo ,  Risa Altaf ,  Richard G. Cliff

发明人： Cameron McClintock ,  Ninh Ngo ,  Risa Altaf ,  Richard G. Cliff

IPC分类号： H01L21/82 ,  H03K19/00 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Each super-region may be like a small or moderately sized programmable logic device and may include a two-dimensional array of intersecting rows and columns of regions of programmable logic. Each region may in turn include a plurality of subregions of programmable logic. Horizontal and vertical inter-super-region interconnection conductors are associated with the rows and columns of super-regions. These conductors are selectively connectable to horizontal and vertical inter-region interconnection conductors in the super-regions.

摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 每个超区域可以像小型或中等尺寸的可编程逻辑器件，并且可以包括可编程逻辑区域的交叉行和列的二维阵列。 每个区域又可以包括多个可编程逻辑的子区域。 水平和垂直超超区域互连导体与超区域的行和列相关联。 这些导体可以选择性地连接到超区域中的水平和垂直的区域间互连导体。

公开(公告)号：US5963049A

公开(公告)日：1999-10-05

申请号：US807561

申请日：1997-02-28

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

公开(公告)号：US5847617A

公开(公告)日：1998-12-08

申请号：US909337

申请日：1997-08-11

申请人： Srinivas T. Reddy ,  David Edward Jefferson ,  Richard G. Cliff ,  Cameron McClintock

发明人： Srinivas T. Reddy ,  David Edward Jefferson ,  Richard G. Cliff ,  Cameron McClintock

IPC分类号： H03K3/03 ,  H03L7/099 ,  H03B5/24

CPC分类号： H03L7/0997 ,  H03K3/0315

摘要： A variable-path-length voltage-controlled oscillator circuit is provided. The oscillator circuit has a ring oscillator formed from a series of voltage-controlled inverter stages. The path length (i.e., the number of inverter stages) in the ring is selected based on path length configuration data stored in memory. The selected path length determines the nominal or center frequency of operation of the ring oscillator. The output frequency of the oscillator circuit is voltage-tuned about this center frequency by varying the delay of each inverter stage in the ring oscillator path. Various types of voltage-controlled inverter stages may be used, including current-starved inverter stages, variable-capacitive-load inverter stages, and differential-delay inverter stages. The voltage-controlled oscillator circuit may be used in a phase-locked loop on a programmable logic device for frequency synthesis or to eliminate clock skew.

摘要翻译： 提供了可变路径长度的压控振荡器电路。 振荡器电路具有由一系列压控逆变器级形成的环形振荡器。 基于存储在存储器中的路径长度配置数据来选择环路的路径长度（即，逆变器级数）。 所选择的路径长度决定了环形振荡器的额定或中心频率。 通过改变环形振荡器路径中每个反相器级的延迟，振荡器电路的输出频率就关于该中心频率进行电压调谐。 可以使用各种类型的压控变频器级，包括电流欠压级，可变容性负载逆变级和差分延迟逆变级。 压控振荡器电路可用于可编程逻辑器件上的锁相环，用于频率合成或消除时钟偏移。

公开(公告)号：US5821787A

公开(公告)日：1998-10-13

申请号：US726461

申请日：1996-10-04

申请人： Cameron McClintock ,  Ninh Ngo

发明人： Cameron McClintock ,  Ninh Ngo

IPC分类号： H03K17/22

CPC分类号： H03K17/223

摘要： A power-on reset (POR) circuit (200) asserts a POR signal when the supply voltage (V.sub.CC) is turned on. As the supply voltage increases, the POR signal is deasserted when the supply voltage reaches a voltage (V.sub.POR1) sufficiently high to make storage elements in a controlled circuit fully operational. The POR signal is kept deasserted until the power supply voltage level drops to a level low enough (V.sub.POR2) to render the storage elements in the controlled circuit incapable of holding accurate data. The V.sub.POR2 level that triggers the reassertion of the POR signal is lower than the V.sub.POR1. Additional circuitry insures that the POR signal is reasserted when V.sub.CC drops to the V.sub.POR2 level by sampling the transistor threshold voltages of the circuit. Another control signal allows the POR signal to be forcibly generated.

摘要翻译： 当电源电压（VCC）导通时，上电复位（POR）电路（200）断言POR信号。 随着电源电压的增加，当电源电压达到足够高的电压（VPOR1）以使受控电路中的存储元件完全运行时，POR信号被置为无效。 POR信号保持断言，直到电源电压电平下降到足够低的水平（VPOR2），以使受控电路中的存储元件不能保存准确的数据。 触发POR信号重新置位的VPOR2电平低于VPOR1。 附加电路确保当VCC通过采样电路的晶体管阈值电压VCC降至VPOR2电平时，重置POR信号。 另一个控制信号允许强制产生POR信号。

公开(公告)号：US5760624A

公开(公告)日：1998-06-02

申请号：US692542

申请日：1996-08-05

申请人： Cameron McClintock

发明人： Cameron McClintock

IPC分类号： H03K3/356 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K3/356008 ,  H03K17/223

摘要： A power-on reset (POR) circuit that initially asserts the POR signal when the supply voltage is turned on. As the supply voltage increases the POR signal is deasserted when it is determined that the supply voltage is sufficiently high to make storage elements in a circuit being controlled by the POR signal fully operational. The POR signal is kept deasserted until the power supply voltage level drops to a level low enough to render the storage elements in the controlled circuit incapable of holding accurate data. The POR signal is then reasserted at this low power supply voltage level. The low power supply voltage level that triggers the reassertion of the POR signal is lower than the sufficiently high power supply voltage level that triggers the deassertion of the POR signal, thus allowing the power supply voltage level to drop significantly before the POR signal is reasserted. A control signal allows the POR signal to be generated in response to different power supply voltage levels. Another control signal allows the POR signal to be forcibly generated.

摘要翻译： 上电复位（POR）电路，当电源电压接通时，它将初始置位POR信号。 当确定供电电压足够高以使电路中的存储元件由POR信号控制完全可操作时，随着电源电压增加，POR信号被断言。 POR信号保持断言，直到电源电压电平下降到足够低的水平，使得受控电路中的存储元件不能保存准确的数据。 然后在该低电源电压电平下重新置位POR信号。 触发POR信号重新置位的低电源电压电平低于触发POR信号失效的足够高的电源电压电平，从而允许电源电压电平在POR信号重新置换之前明显下降。 控制信号允许响应于不同的电源电压电平而产生POR信号。 另一个控制信号允许强制产生POR信号。

公开(公告)号：US5612642A

公开(公告)日：1997-03-18

申请号：US430923

申请日：1995-04-28

申请人： Cameron McClintock

发明人： Cameron McClintock

IPC分类号： H03K3/356 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K3/356008 ,  H03K17/223

摘要： A power-on reset (POR) circuit that initially asserts the POR signal when the supply voltage is turned on. As the supply voltage increases the POR signal is deasserted when it is determined that the supply voltage is sufficiently high to make storage elements in a circuit being controlled by the POR signal fully operational. The POR signal is kept deasserted until the power supply voltage level drops to a level low enough to render the storage elements in the controlled circuit incapable of holding accurate data. The POR signal is then reasserted at this low power supply voltage level. The low power supply voltage level that triggers the reassertion of the POR signal is lower than the sufficiently high power supply voltage level that triggers the deassertion of the POR signal, thus allowing the power supply voltage level to drop significantly before the POR signal is reasserted. A control signal allows the POR signal to be generated in response to different power supply voltage levels. Another control signal allows the POR signal to be forcibly generated.

摘要翻译： 上电复位（POR）电路，当电源电压接通时，它将初始置位POR信号。 当确定电源电压足够高以使电路中的存储元件被POR信号控制完全可操作时，随着电源电压增加，POR信号被断言。 POR信号保持断言，直到电源电压电平下降到足够低的水平，使得受控电路中的存储元件不能保存准确的数据。 然后在该低电源电压电平下重新置位POR信号。 触发POR信号重新置位的低电源电压电平低于触发POR信号失效的足够高的电源电压电平，从而允许电源电压电平在POR信号重新置换之前明显下降。 控制信号允许响应于不同的电源电压电平而产生POR信号。 另一个控制信号允许强制产生POR信号。

公开(公告)号：US5606276A

公开(公告)日：1997-02-25

申请号：US319381

申请日：1994-10-05

申请人： Cameron McClintock

发明人： Cameron McClintock

IPC分类号： H03K5/135 ,  H03K5/1534 ,  H03K5/26 ,  H03D13/00

CPC分类号： H03K5/135 ,  H03K5/1534 ,  H03K5/26

摘要： A delay element (10) generates a delay pulse (OUT) the length of which is not dependent on an available system clock. The delay element uses oscillators (12a, 12b, 12c) and edge detectors (16a, 16b, 16c) to generate a delay based on the beat frequency of the oscillators. The delay element is suitable for fabrication as part of a CMOS integrated circuit, and requires less layout area than alternative methods.

摘要翻译： 延迟元件（10）产生其长度不依赖于可用的系统时钟的延迟脉冲（OUT）。 延迟元件使用振荡器（12a，12b，12c）和边缘检测器（16a，16b，16c）来产生基于振荡器的拍频的延迟。 延迟元件适用于制造CMOS集成电路的一部分，并且比替代方法需要较少的布局面积。