公开(公告)号：US5477413A

公开(公告)日：1995-12-19

申请号：US187746

申请日：1994-01-26

申请人： Jeffrey T. Watt

发明人： Jeffrey T. Watt

IPC分类号： H01L27/02 ,  H02H9/04

CPC分类号： H01L27/0251

摘要： An ESD protection structure for p-well technology using nMOS FETs that prevents the lock-on condition normally occurring after one FET of a multi finger structure snaps back. The multifinger structure is contained in a main p-well and channels ESDs of a first polarity from the contact pad to a metal conduit. A resistance is provided between the main p-well and the conduit. Further, the circuit channeling ESDs of a polarity opposite to the first polarity is contained in a second p-well that is distinct from the main p-well. An ESD event causes one of the fingers to snap back. Resulting drain current through that finger generates electron hole pairs in the main p-well by impact ionization. Thus generated holes, traveling to the conduit through the resistance, raise the voltage of the main p-well, and therefore shift the i-v characteristic curves of all the FETs to a point where they no longer exhibit a knee. The absence of a knee prevents the remaining fingers from being locked off by the finger that snapped back. Consequently, all FETs are turned on and ESD protection is provided by all FETs in the main p-well.

摘要翻译： 使用nMOS FET的p阱技术的ESD保护结构，防止在多指结构的一个FET捕获之后通常发生的锁定状态。 多焦点结构包含在主p阱中，并且将从接触垫到金属导管的第一极性的通道ESD。 在主p阱和导管之间提供电阻。 此外，与第一极性相反的极性的电路通道ESD被包含在与主p阱不同的第二p阱中。 ESD事件导致其中一根手指回弹。 通过该手指产生的漏极电流通过冲击电离在主p阱中产生电子空穴对。 因此产生的孔通过电阻传导到导管，提高了主p阱的电压，因此将所有FET的i-v特性曲线转移到不再显示膝盖的点。 没有膝盖可防止剩余的手指被卡扣的手指锁定。 因此，所有FET都导通，ESD保护由主p阱中的所有FET提供。

公开(公告)号：US08797790B1

公开(公告)日：2014-08-05

申请号：US12568638

申请日：2009-09-28

申请人： Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  William Bradley Vest

发明人： Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  William Bradley Vest

IPC分类号： G11C11/00 ,  G11C11/412 ,  G11C8/16

CPC分类号： G11C11/412 ,  G11C5/005 ,  G11C5/06 ,  G11C8/16 ,  G11C11/4125

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.

摘要翻译： 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 每个存储元件可以各自具有形成双稳态元件，一对地址晶体管和连接在两个逆变器之间的一对相对较弱的晶体管的四个逆变器状晶体管对，其形成公共输出节点，其抵抗快速变化 它的状态。 晶体管可以以形成双稳态存储器元件的图案连接，该双稳态存储器元件由于辐射打击而抵抗软错误不正常事件。 可以使用地址晶体管对将数据加载到存储器元件中并从存储器元件读出。

公开(公告)号：US08716809B2

公开(公告)日：2014-05-06

申请号：US13338701

申请日：2011-12-28

申请人： Andy L. Lee ,  Jeffrey T. Watt

发明人： Andy L. Lee ,  Jeffrey T. Watt

IPC分类号： H01L21/70

CPC分类号： H03K19/173 ,  G11C5/005 ,  H01L27/0207 ,  H03K19/1736 ,  H03K19/17784

摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

摘要翻译： 硬化可编程逻辑器件提供有可编程电路。 可编程电路可以是硬连线的，以实现定制逻辑电路。 可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。 可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。 可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

公开(公告)号：US08461869B1

公开(公告)日：2013-06-11

申请号：US13214147

申请日：2011-08-19

申请人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

发明人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

IPC分类号： H03K19/003

CPC分类号： H03K19/003 ,  H03K19/17784

摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

摘要翻译： 一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。 温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号 调节器 所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。

公开(公告)号：US20130127494A1

公开(公告)日：2013-05-23

申请号：US13304226

申请日：2011-11-23

申请人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

发明人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

IPC分类号： H03K19/177 ,  G11C11/52

CPC分类号： G11C11/52 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  H01H1/0094 ,  H01H1/20 ,  H01H59/0009 ,  H01L27/101 ,  H01L27/11

摘要： Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

摘要翻译： 提供具有存储元件的集成电路。 集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分， 中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。 第一和第二部分中的装置可以接收相应的电源电压。 在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。 在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。 第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。 以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

公开(公告)号：US08217461B1

公开(公告)日：2012-07-10

申请号：US12833864

申请日：2010-07-09

申请人： Charles Y. Chu ,  Jeffrey T. Watt

发明人： Charles Y. Chu ,  Jeffrey T. Watt

IPC分类号： H01L23/62

CPC分类号： H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-fingered gate transistor is disclosed that is formed in a substrate of one conductivity type overlying a well of a second conductivity type. Ohmic contact to the well is made by an implanted region of the second conductivity type that circumscribes the multi-fingered gate transistor. Ohmic contact to the substrate is made by four taps located on four sides of the multi-fingered gate structure between the gate structure and the well contact. Floating wells are located on opposite sides of the gate structure between two of the substrate taps and the ends of the gates to isolate these substrate taps and force current flow in the substrate under the multifingered gate transistor to be substantially perpendicular to the direction in which the gate fingers extend. This increases the potential difference between these substrate regions and adjacent source regions in the multi-fingered gate transistor, thereby aiding the triggering of the parasitic bipolar transistors under adjacent gate fingers into a high current state. This also reduces the differences among the potentials in the substrate under the different source regions and thus improves the uniformity of turn-on of the parasitic bipolar transistors. As a result, it is not necessary to maintain as great a distance from the isolated substrate taps as in prior art devices. Moreover, because the floating wells significantly improve the performance of the ESD protection structure, some of this performance improvement may be exchanged for decreases in the size of the protection structure.

摘要翻译： 公开了一种多指栅极晶体管，其形成在覆盖第二导电类型的阱的一种导电类型的衬底中。 与阱的欧姆接触由外接多指栅极晶体管的第二导电类型的注入区域制成。 通过在门结构和阱接触之间的多指门结构的四侧上的四个抽头来形成与基板的欧姆接触。 浮动阱位于栅极结构的两个基板抽头和栅极端之间的相对侧上，以隔离这些基板抽头并迫使多栅极晶体管下方的衬底中的电流大致垂直于 门指延伸。 这增加了多指栅极晶体管中的这些衬底区域和相邻源极区域之间的电位差，从而有助于在相邻栅极指状态下的寄生双极晶体管的触发成高电流状态。 这也减少了在不同源极区域下的衬底中的电位之间的差异，从而提高了寄生双极晶体管的导通的均匀性。 结果，与现有技术的装置相比，不需要保持与隔离的基板抽头相距很远的距离。 此外，由于浮动阱显着改善了ESD保护结构的性能，因此可以交换一些这种性能改进以减小保护结构的尺寸。

公开(公告)号：US20120032702A1

公开(公告)日：2012-02-09

申请号：US12852422

申请日：2010-08-06

申请人： Andy L. Lee ,  Jeffrey T. Watt

发明人： Andy L. Lee ,  Jeffrey T. Watt

IPC分类号： H03K19/0175 ,  G06F17/50 ,  H03K19/00 ,  H01L21/82

CPC分类号： H03K19/173 ,  G11C5/005 ,  H01L27/0207 ,  H03K19/1736 ,  H03K19/17784

摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

摘要翻译： 硬化可编程逻辑器件提供有可编程电路。 可编程电路可以是硬连线的，以实现定制逻辑电路。 可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。 可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。 可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

公开(公告)号：US08057964B2

公开(公告)日：2011-11-15

申请号：US12263413

申请日：2008-10-31

申请人： Che Ta Hsu ,  Peter J. McElheny ,  Jeffrey T. Watt

发明人： Che Ta Hsu ,  Peter J. McElheny ,  Jeffrey T. Watt

IPC分类号： G03F1/00 ,  H01L23/62

CPC分类号： G03F1/40

摘要： Photolithographic reticles are provided that have electrostatic discharge protection features. A photolithographic reticle may be formed from metal structures such as chrome structures on a transparent substrate such as fused silica. Some of the metal structures on the reticle correspond to transistors and other electronic devices on integrated circuits that are fabricated when using the reticles in a step-and-repeat lithography tool. These metal device structures may be susceptible to damage due to electrostatic charge build up during handling of the reticle. To prevent damage, dummy ring structures are formed in the vicinity of device structures. The dummy ring structures may be constructed to be more sensitive to electrostatic discharge than the device structures, so that in the event of an electrostatic discharge, damage is confined to portions of the reticle that are not critical.

摘要翻译： 提供具有静电放电保护特征的光刻掩模版。 光刻掩模版可以由诸如熔融二氧化硅的透明基板上的诸如铬结构的金属结构形成。 掩模版上的一些金属结构对应于在步进重复光刻工具中使用掩模版时制造的集成电路上的晶体管和其他电子器件。 这些金属器件结构可能由于在掩模版的处理过程中由于静电电荷的积累而易于损坏。 为了防止损坏，在设备结构附近形成虚拟环结构。 伪环结构可以被构造成比器件结构对静电放电更敏感，使得在静电放电的情况下，损坏被限制在不太关键的掩模版的部分上。

公开(公告)号：US07902953B1

公开(公告)日：2011-03-08

申请号：US12228956

申请日：2008-08-18

申请人： Jeffrey T. Watt

发明人： Jeffrey T. Watt

IPC分类号： H01F5/00

CPC分类号： H01F5/003 ,  H01F2027/2838

摘要： A spiral inductor includes a winding that includes a plurality of strands. The spiral inductor also includes a plurality of tracks where a first set of tracks is positioned adjacent to one another on a first of layer and a second set of tracks is positioned adjacent to one another on a second layer. Each of the plurality of tracks is capable of supporting one of the plurality of strands. The spiral inductor also includes a plurality of crossing segments to transpose one or more of the plurality of strands to each of the plurality of tracks, wherein each of the plurality of strands is electrically isolated from the other plurality of strands.

摘要翻译： 螺旋电感器包括包括多个绞线的绕组。 螺旋电感器还包括多个磁道，其中第一组磁道在第一层上彼此相邻地定位，并且第二组磁道在第二层上彼此相邻地定位。 多个轨道中的每一个能够支撑多个股线之一。 螺旋电感器还包括多个交叉部分，用于将多个股线中的一个或多个股转置到多个轨道中的每一个，其中多个股线中的每一个与其它多个股线电隔离。

公开(公告)号：US20100321984A1

公开(公告)日：2010-12-23

申请号：US12868575

申请日：2010-08-25

申请人： Irfan Rahim ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest ,  Jeffrey T. Watt

发明人： Irfan Rahim ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest ,  Jeffrey T. Watt

IPC分类号： G11C11/24

CPC分类号： H03K19/1776 ,  G11C11/401 ,  G11C11/404 ,  G11C14/00 ,  H03K19/1778

摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.

摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。