公开(公告)号：US20220068813A1

公开(公告)日：2022-03-03

申请号：US17006695

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H01L23/528 ,  H01L27/06 ,  H03K19/0185

Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.

公开(公告)号：US20220068346A1

公开(公告)日：2022-03-03

申请号：US17006689

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: G11C11/4074 ,  G11C11/4094 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/10

Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.

公开(公告)号：US11087834B2

公开(公告)日：2021-08-10

申请号：US16555899

申请日：2019-08-29

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Pratik Ghanshambhai Satasia

IPC: G11C11/00 ,  G11C11/419 ,  H03K5/24 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having various circuitry for reading first data from a memory location in single-port memory and writing second data to the memory location in the single-port memory after reading the first data from the memory location. In some implementations, reading the first data and writing the second data to the memory location are performed in a single operation.

公开(公告)号：US11056183B2

公开(公告)日：2021-07-06

申请号：US15961862

申请日：2018-04-24

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/418 ,  H01L27/11

Abstract: Various implementations described herein are directed to an integrated circuit having multiple bitcell arrays and multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays. The integrated circuit may include multiple read output ports for the multiple bitcell arrays. The single write input port is used for writing data to the multiple bitcell arrays, and the multiple read input ports are used separately for reading data from the multiple bitcell arrays for output to the multiple read output ports.

公开(公告)号：US10937481B1

公开(公告)日：2021-03-02

申请号：US16534942

申请日：2019-08-07

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Peixuan Tan

IPC: G11C5/06 ,  G11C7/18 ,  G11C7/10 ,  G11C11/16 ,  G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having memory circuitry having bitcells coupled together via bitlines. The device may include polarity swapping circuitry having multiple conductive paths that are configured to couple the bitlines together. In some instances, first paths of the multiple conductive paths couple the bitlines together via first passgates, and second paths of the multiple conductive paths couple the bitlines together via second passgates.

公开(公告)号：US20210043241A1

公开(公告)日：2021-02-11

申请号：US16534942

申请日：2019-08-07

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Peixuan Tan

IPC: G11C11/16 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are directed to a device having memory circuitry having bitcells coupled together via bitlines. The device may include polarity swapping circuitry having multiple conductive paths that are configured to couple the bitlines together. In some instances, first paths of the multiple conductive paths couple the bitlines together via first passgates, and second paths of the multiple conductive paths couple the bitlines together via second passgates.

公开(公告)号：US20210019463A1

公开(公告)日：2021-01-21

申请号：US17062567

申请日：2020-10-03

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Gus Yeung ,  Marlin Wayne Frederick, JR. ,  Sriram Thyagarajan

IPC: G06F30/39 ,  G06F30/30 ,  G06F30/398

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US20190325962A1

公开(公告)日：2019-10-24

申请号：US15959048

申请日：2018-04-20

Applicant: Arm Limited

Inventor： Mohammed Saif Kunjatur Sheikh ,  Vikash ,  Andy Wangkun Chen

IPC: G11C15/04 ,  G06F11/10 ,  G11C29/42

Abstract: Various implementations described herein are directed to an integrated circuit having an array of bitcells. The integrated circuit may include latch circuitry having a latch for each row of bitcells that latches valid match data into the latch for each row of bitcells. The integrated circuit may include priority encoding circuitry that receives the valid match data from the latch for each row of bitcells. The integrated circuit may include first logic circuitry coupled between the array of bitcells and the priority encoding circuitry to assist with providing the valid match data to the latch circuitry.

公开(公告)号：US10177760B1

公开(公告)日：2019-01-08

申请号：US15636428

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Yicong Li ,  Hsin-Yu Chen ,  Sriram Thyagarajan

IPC: G11C5/06 ,  H03K17/687 ,  G11C5/14 ,  H01L23/64 ,  G11C7/10 ,  G06F17/50 ,  G11C8/08

Abstract: A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.

公开(公告)号：US20180225402A9

公开(公告)日：2018-08-09

申请号：US14528314

申请日：2014-10-30

Applicant: ARM Limited

Inventor： Paul DE DOOD ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Douglas Ngai Lee ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Yanbin Jiang ,  Emmanuel Jean Marie Olivier Pacaud ,  Matthieu Domonique Henri Pauly ,  Sylvia Xiuhui Li ,  Thanusree Achuthan ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.