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    Error detection circuitry for use with memory
    52.
    发明授权
    Error detection circuitry for use with memory 有权

    公开(公告)号：US09891976B2

    公开(公告)日：2018-02-13

    申请号：US14633062

    申请日：2015-02-26

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Mudit Bhargava ,  Paul Gilbert Meyer ,  Vikas Chandra

    IPC: G06F11/10 ,  G06F11/07 ,  G06F11/08

    CPC classification number: G06F11/076 ,  G06F11/085 ,  G06F11/1012 ,  G06F11/1016

    Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

    TSV coupled integrated circuits and methods
    56.
    发明授权
    TSV coupled integrated circuits and methods 有权

    公开(公告)号：US11569219B2

    公开(公告)日：2023-01-31

    申请号：US17077532

    申请日：2020-10-22

    Applicant: Arm Limited

    Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

    IPC: H01L27/02 ,  G06F30/31 ,  H01L21/768 ,  H01L23/535 ,  H01L25/065 ,  H01L25/00

    Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

    Memory for an artificial neural network accelerator
    57.
    发明授权
    Memory for an artificial neural network accelerator 有权

    公开(公告)号：US11526305B2

    公开(公告)日：2022-12-13

    申请号：US17103629

    申请日：2020-11-24

    Applicant: Arm Limited

    Inventor： Mudit Bhargava ,  Paul Nicholas Whatmough ,  Supreet Jeloka ,  Zhi-Gang Liu

    IPC: G06F3/06 ,  G06N3/063

    Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of read word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each read word selector has a plurality of input ports and an output port, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the read word selectors of the first bank and the second bank, and configured to select a combination of read word selectors from at least one of the first bank and the second bank based on a bank select signal.

    Ramp Write Techniques
    58.
    发明申请
    Ramp Write Techniques 有权

    公开(公告)号：US20220172762A1

    公开(公告)日：2022-06-02

    申请号：US17107725

    申请日：2020-11-30

    Applicant: Arm Limited

    Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Pranay Prabhat ,  Femando Garcia Redondo

    IPC: G11C11/16

    Abstract: Various implementations described herein are related to a method. The method may apply a write control voltage to a bitcell. The method may gradually ramp the write control voltage to the bitcell. The method may terminate application of the write control voltage to the bitcell when a write operation is sensed in the bitcell.

    CAM device with 3D CAM cells
    59.
    发明授权
    CAM device with 3D CAM cells 有权

    公开(公告)号：US11211111B1

    公开(公告)日：2021-12-28

    申请号：US17038795

    申请日：2020-09-30

    Applicant: Arm Limited

    Inventor： Rahul Mathur ,  Mudit Bhargava ,  Supreet Jeloka ,  Andy Wangkun Chen

    IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/4094 ,  G11C5/02 ,  G11C15/04 ,  G11C11/4097

    Abstract: A content-addressable memory (CAM) storage element includes bit storage cell bit comparison cells. The bit storage cell is arranged on a first die tier and includes at least one transistor, one or two bit lines, and a storage node. The bit comparison cell is arranged on a second die tier and has a match line, complementary search lines, and at least three transistors. The complementary search lines are decoupled from the bit line(s). A 3D connection couples the storage node to one of the transistors of the second die tier. The CAM cell performs at least one CAM search per clock cycle using at least four transistors per search, including the at least one transistor of the bit storage cell and the at least three transistors of the bit comparison cell, and to output results of the at least one CAM search on the match line.

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