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739 条记录 (耗时 0.044 秒)

    MEMORY RESISTOR HAVING MULTI-LAYER ELECTRODES
    54.
    发明申请
    MEMORY RESISTOR HAVING MULTI-LAYER ELECTRODES 有权
    具有多层电极的记忆电阻

    公开(公告)号：US20120120714A1

    公开(公告)日：2012-05-17

    申请号：US13387063

    申请日：2010-02-08

    申请人： Jianhua Yang ,  Wei Wu ,  Gilberto Ribeiro

    发明人： Jianhua Yang ,  Wei Wu ,  Gilberto Ribeiro

    IPC分类号： G11C11/00 ,  H01L45/00

    CPC分类号： H01L45/08 ,  G11C13/0002 ,  H01L45/1253 ,  H01L45/146

    摘要： Methods and means related to memory resistors are provided. A memristor includes two multi-layer electrodes and an active material layer. One multi-layer electrode forms an Ohmic contact region with the active material layer. The other multi-layer electrode forms a Schottky barrier layer with the active material layer. The active material layer is subject to oxygen vacancy profile reconfiguration under the influence of an applied electric field. An electrical resistance of the memristor is thus adjustable by way of applied programming voltages and is non-volatile between programming events.

    摘要翻译： 提供了与存储电阻相关的方法和方法。 忆阻器包括两个多层电极和活性材料层。 一个多层电极与活性材料层形成欧姆接触区域。 其他多层电极与活性物质层形成肖特基势垒层。 在施加的电场的影响下，活性物质层经受氧空位轮廓重构。 因此，忆阻器的电阻可以通过施加的编程电压进行调节，并且在编程事件之间是非易失性的。

    Mechanism for 3rd Generation Partnership Project Multiple Inter-Network Quality of Service Continuity
    56.
    发明申请
    Mechanism for 3rd Generation Partnership Project Multiple Inter-Network Quality of Service Continuity 审中-公开
    第三代合作伙伴计划机制多网络服务质量连续性

    公开(公告)号：US20120093129A1

    公开(公告)日：2012-04-19

    申请号：US13336978

    申请日：2011-12-23

    申请人： Xiaoming Zhao ,  Wei Wu

    发明人： Xiaoming Zhao ,  Wei Wu

    IPC分类号： H04W36/00

    CPC分类号： H04W28/22 ,  H04W36/00 ,  H04W36/0033 ,  H04W36/0044 ,  H04W36/14

    摘要： A system to promote connectivity for inter-radio access technology (RAT) handover from a first radio access network (RAN) to a second radio access network (RAN) is provided. The system comprises a component configured such that for each access point name (APN) in communication with the first radio access network (RAN), the maximum bit rate (MBR) for each active non-guaranteed bit rate (non-GBR) bearer in the second radio access network (RAN) is determined based on each respective access point name's (APN's) used aggregate maximum bit rate (AMBR) and the number of active non-guaranteed bit rate(s) (non-GBR) bearers for the respective access point name (APN).

    摘要翻译： 提供了一种用于促进从第一无线电接入网（RAN）到第二无线电接入网（RAN）的无线电接入技术（RAT）切换的连接的系统。 该系统包括被配置为使得对于与第一无线电接入网络（RAN）通信的每个接入点名称（APN），每个主动非保证比特率（非GBR）承载的最大比特率（MBR） 基于每个相应的接入点名称（APN）使用的聚合最大比特率（AMBR）和相应的各个接入点名称的有效非保证比特率（非GBR）承载的数量确定第二无线电接入网络（RAN） 接入点名称（APN）。

    Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays
    59.
    发明授权
    Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays 有权
    用于实现位于横杆阵列的纳米线交叉点处的自旋电子器件的逻辑门的方法和系统

    公开(公告)号：US08143682B2

    公开(公告)日：2012-03-27

    申请号：US11590959

    申请日：2006-10-31

    申请人： Alexandre M. Bratkovski ,  Wei Wu ,  Gregory S. Snider ,  R. Stanley Williams

    发明人： Alexandre M. Bratkovski ,  Wei Wu ,  Gregory S. Snider ,  R. Stanley Williams

    IPC分类号： H01L29/82

    CPC分类号： H03K19/18 ,  B82Y10/00 ,  H01L27/22 ,  H03K3/45

    摘要： Various method and system embodiments of the present invention are directed to implementing serial logic gates using nanowire-crossbar arrays with spintronic devices located at nanowire-crossbar junctions. In one embodiment of the present invention, a nanowire-crossbar array comprises a first nanowire and a number of substantially parallel control nanowires positioned so that each control nanowire overlaps the first nanowire. The nanowire-crossbar array includes a number of spintronic devices. Each spintronic device is configured to connect one of the control nanowires to the first nanowire and operate as a latch for controlling signal transmissions between the control nanowire and the first nanowire.

    摘要翻译： 本发明的各种方法和系统实施例涉及使用位于纳米线交叉点处的自旋电子器件的纳米线交叉阵列来实现串行逻辑门。 在本发明的一个实施例中，纳米线交叉串阵列包括第一纳米线和多个基本上平行的控制纳米线，所述纳米线被定位成使得每个对照纳米线与第一纳米线重叠。 纳米线交叉开关阵列包括许多自旋电子器件。 每个自旋电子设备被配置为将控制纳米线中的一个连接到第一纳米线并且用作用于控制控制纳米线和第一纳米线之间的信号传输的锁存器。

    Negative index material-based modulators and methods for fabricating the same
    60.
    发明授权
    Negative index material-based modulators and methods for fabricating the same 有权
    负基于材料的调制剂及其制造方法

    公开(公告)号：US08107149B2

    公开(公告)日：2012-01-31

    申请号：US12387169

    申请日：2009-04-29

    申请人： Wei Wu ,  Alexandre M. Bratkovski ,  Shih-Yuan Wang ,  Jingjing Li ,  Qiangfei Xia

    发明人： Wei Wu ,  Alexandre M. Bratkovski ,  Shih-Yuan Wang ,  Jingjing Li ,  Qiangfei Xia

    IPC分类号： G02B26/00 ,  G02F1/01

    CPC分类号： G02F1/01 ,  G02F3/02 ,  G02F2202/30 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/949 ,  Y10S977/95

    摘要： Various embodiments of the present invention are directed to external, electronically controllable, negative index material-based modulators. In one aspect, an external modulator comprises a negative index material in electronic communication with an electronic signal source. The negative index material receives an electronic signal encoding data from the electronic signal source and an unmodulated carrier wave from an electromagnetic radiation source. Magnitude variations in the electronic signal produce corresponding effective refractive index changes in the negative index material encoding the data in the amplitude and/or phase of the carrier wave to produce an electromagnetic signal.

    摘要翻译： 本发明的各种实施方案涉及外部的，电子可控的，负指数材料的调节剂。 一方面，外部调制器包括与电子信号源电子通信的负索引材料。 负索引材料接收来自电子信号源的电子信号编码数据和来自电磁辐射源的未调制载波。 电子信号的幅度变化在编码载波的幅度和/或相位中的数据的负指数材料中产生对应的有效折射率变化，以产生电磁信号。