公开(公告)号：US07110286B2

公开(公告)日：2006-09-19

申请号：US10919371

申请日：2004-08-17

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US06928022B2

公开(公告)日：2005-08-09

申请号：US10969697

申请日：2004-10-20

申请人： Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： G11C13/02 ,  G11C13/00 ,  G11C16/02 ,  G11C16/12 ,  G11C16/30 ,  G11C29/02 ,  H01L27/105 ,  H01L45/00 ,  G11C17/18

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0038 ,  G11C29/02 ,  G11C29/028 ,  G11C2013/0078 ,  G11C2029/5006 ,  G11C2213/79

摘要： A write driver circuit including a plurality of programmable fuses for a phase change memory device in which a write operation is correctly performed even in the case where a current output shift in a write current generation circuit; or in the case where a phase change memory cell having a phase change property shift due to an external factor or due a process change. The write driver circuit includes a write current control unit for outputting a first or second level of voltage selected, by selecting one of a first or second programmable current path, based on whether a first or second selection pulse signal is applied; and a current driving unit for generating a write current controlled by the output voltage of the write current control unit. Each of the first and second programmable current paths includes fuses that can be programmed to adjust their resistance to adjust the respective selected output voltage to compensate for the current output shift in the write current generation circuit or for the phase change memory cell having the phase change property shift.

摘要翻译： 一种写入驱动器电路，包括用于相变存储器件的多个可编程保险丝，其中即使在写入电流产生电路中的电流输出移位的情况下也正确地执行写入操作; 或者由于外部因素或由于处理变化而具有相变特性偏移的相变存储单元的情况。 写入驱动器电路包括：写入电流控制单元，用于通过选择第一或第二可选择电流路径中的一个，基于是否应用第一或第二选择脉冲信号来输出所选择的第一或第二电平电平; 以及电流驱动单元，用于产生由写入电流控制单元的输出电压控制的写入电流。 第一和第二可编程电流路径中的每一个包括熔丝，其可以被编程以调整其电阻以调整相应的选择的输出电压以补偿写入电流产生电路中的电流输出偏移或具有相变的相变存储器单元 财产转移

公开(公告)号：US20110188303A1

公开(公告)日：2011-08-04

申请号：US13064672

申请日：2011-04-07

申请人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

发明人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

摘要翻译： 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

公开(公告)号：US07936612B2

公开(公告)日：2011-05-03

申请号：US12654338

申请日：2009-12-17

申请人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

发明人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

摘要翻译： 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

公开(公告)号：US07889548B2

公开(公告)日：2011-02-15

申请号：US12585637

申请日：2009-09-21

申请人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Ji-Hye Yi ,  Beak-Hyung Cho

发明人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Ji-Hye Yi ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

摘要： According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure.

摘要翻译： 根据一个实施方案，包括第一结晶相的至少一部分相变材料转化为第二结晶相和非晶相之一。 第二结晶相比第一结晶相更容易转变成非晶态。 例如，第一结晶相可以是六方密封填充结构，并且第一结晶相可以是面心立方结构。

公开(公告)号：US20100097850A1

公开(公告)日：2010-04-22

申请号：US12611606

申请日：2009-11-03

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.

摘要翻译： 提供了使用相变存储器件的装置和系统。 相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。 每个顺序复位脉冲被输出到多个复位线中相应的一个。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

公开(公告)号：US20090316474A1

公开(公告)日：2009-12-24

申请号：US12457319

申请日：2009-06-08

申请人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

发明人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

IPC分类号： G11C11/00 ,  G11C29/00

CPC分类号： G11C29/808 ,  G11C13/0004

摘要： The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

摘要翻译： 所述相变存储器件包括多个存储体，连接到所述多个存储体的多个局部导体线，连接到所述多个局部导体线的至少一个全局导体线，以及至少一个修理控制电路， 选择性地将所述至少一个全局导体线中的至少一个与至少一个冗余全局导体线替换并且被配置为用至少一个冗余局部导体线选择性地替换所述多条局部导体线中的至少一个。

公开(公告)号：US20080106922A1

公开(公告)日：2008-05-08

申请号：US11735635

申请日：2007-04-16

申请人： Joon-Min Park ,  Byung-Gil Choi ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Joon-Min Park ,  Byung-Gil Choi ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C5/06 ,  G11C11/00

CPC分类号： G11C11/16 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/76

摘要： A semiconductor memory device and a layout structure of word line contacts, in which the semiconductor memory device includes an active region, a plurality of memory cells, and word line contacts. The active region is disposed in a first direction as a length direction on a semiconductor substrate and is used as a word line. The plurality of memory cells are disposed in the first direction on the active region and are each constructed of one variable resistance device and one diode device. In the word line contacts, at least one each is disposed between respective units, wherein each unit is constructed of predetermined numbers of memory cells on the active region. A bridge effect, such as a short-circuit between adjacent word lines, can be prevented or substantially reduced.

摘要翻译： 半导体存储器件和字线触点的布局结构，其中半导体存储器件包括有源区，多个存储单元和字线触点。 有源区域沿着半导体衬底上的长度方向的第一方向设置，并用作字线。 多个存储单元在有源区域上沿第一方向设置，并且分别由一个可变电阻器件和一个二极管器件构成。 在字线触点中，每个单元之间至少设置一个，其中每个单元由有源区上的预定数量的存储单元构成。 可以防止或显着减少诸如相邻字线之间的短路的桥接效应。

公开(公告)号：US07304885B2

公开(公告)日：2007-12-04

申请号：US11074557

申请日：2005-03-08

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Phase-change memory devices are provided that include a plurality of phase-change memory cells and a reset pulse generation circuit configured to output a plurality of sequential reset pulses. Each sequential reset pulse is output to a corresponding one of a plurality of reset lines. A plurality of write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit. Methods of programming phase-change memory devices using sequential reset control signals are also provided.

摘要翻译： 提供了包括多个相变存储器单元的相变存储器件和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。 每个顺序复位脉冲被输出到多条复位线中相应的一条。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。 还提供了使用顺序复位控制信号编程相变存储器件的方法。

公开(公告)号：US20070189104A1

公开(公告)日：2007-08-16

申请号：US11787931

申请日：2007-04-18

申请人： Beak-Hyung Cho ,  Du-Eung Kim

发明人： Beak-Hyung Cho ,  Du-Eung Kim

IPC分类号： G11C8/00

CPC分类号： G11C13/0028 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004

摘要： A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.

摘要翻译： 存储器件包括多个块，每个块具有相应的存储器单元阵列和相应的本地字线。 存储器件还包括耦合在每个本地字线和公共电压节点之间的相应开关器件。 全局字线驱动器控制相应的开关装置对跨越包括访问的存储器单元的块的行中的相应本地字线导通。 因此，公共电压节点处于被访问的存储器单元的当前路径中，具有最小的布局面积和当前路径的电阻。