公开(公告)号：US20070252241A1

公开(公告)日：2007-11-01

申请号：US11767635

申请日：2007-06-25

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/94 ,  H01L21/336 ,  H01L29/76 ,  H01L29/06

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

公开(公告)号：US20070249130A1

公开(公告)日：2007-10-25

申请号：US11379581

申请日：2006-04-21

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/26586 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7851

摘要： Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the semiconductor fin. Specifically, a protective cap layer is formed above the source/drain regions of the fin in order to protect those regions during a subsequent amporphization ion implantation process. The fin is further protected, during this implantation process, because the ion beam is directed towards the gate in a plane that is parallel to the fin and tilted from the vertical axis. Thus, amorphization of the fin and damage to the fin are limited. Following the implantation process and the formation of a straining layer, a recrystallization anneal is performed so that the strain of the straining layer is ‘memorized’ in the polysilicon gate.

摘要翻译： 公开了一种用于在非平面FET（例如，finFET或触发FET）的多晶硅栅极中诱导应变的技术，以便在FET沟道区上施加类似的应变，同时保护FET的源极/漏极区域 半导体鳍片 具体地，在翅片的源极/漏极区域之上形成保护盖层，以便在随后的悬空离子注入工艺期间保护这些区域。 在该植入过程期间，翅片被进一步保护，因为离子束在平行于翅片并从垂直轴倾斜的平面中朝向栅极。 因此，翅片的非晶化和鳍的损害是有限的。 在注入工艺和形成应变层之后，进行再结晶退火，使得应变层的应变“存储在多晶硅栅极中”。

公开(公告)号：US20070224743A1

公开(公告)日：2007-09-27

申请号：US11756078

申请日：2007-05-31

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

IPC分类号： H01L21/84

CPC分类号： H01L29/78606 ,  H01L27/0248 ,  H01L29/42384 ,  H01L29/785

摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.

摘要翻译： 翅片型场效应晶体管具有在衬底上方的绝缘体层和在绝缘体层上方延伸的翅片。 鳍片有一个通道区域，以及源极和漏极区域。 栅极导体位于沟道区域的上方。 绝缘体层包括邻近翅片的散热结构特征，并且栅极导体的一部分接触散热结构特征。 散热结构特征可以包括绝缘体层内的凹槽或延伸穿过绝缘体层的热导体。

公开(公告)号：US20070188195A1

公开(公告)日：2007-08-16

申请号：US11276169

申请日：2006-02-16

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H03K19/0175

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.

摘要翻译： 提供了一种用于提供用于集成电路芯片的多电压岛/核心架构的驱动器的系统和方法。 互补金属氧化物半导体（CMOS）逆变器由高阈值电压p沟道场效应晶体管（hi-Vt PFET）和规则阈值电压n沟道场效应晶体管（NFET）构成，其使用最大正值 电源（Vdd）在芯片上。 基于最大Vdd，驱动CMOS反相器的电压岛/芯的Vdd和hi-Vt PFET的亚阈值泄漏电流要求来确定hi-Vt PFET的阈值电压。

公开(公告)号：US20070134864A1

公开(公告)日：2007-06-14

申请号：US11671795

申请日：2007-02-06

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/66803

摘要： Disclosed is a structure and method for producing a fin-type field effect transistor (FinFET) that has a buried oxide layer over a substrate, at least one first fin structure and at least one second fin structure positioned on the buried oxide layer. First spacers are adjacent the first fin structure and second spacers are adjacent the second fin structure. The first spacers cover a larger portion of the first fin structure when compared to the portion of the second fin structure covered by the second spacers. Those fins that have larger spacers will receive a smaller area of semiconductor doping and those fins that have smaller spacers will receive a larger area of semiconductor doping. Therefore, there is a difference in doping between the first fins and the second fins that is caused by the differently sized spacers. The difference in doping between the first fins and the second fins changes an effective width of the second fins when compared to the first fins.

摘要翻译： 公开了一种用于制造在衬底上具有掩埋氧化层的鳍式场效应晶体管（FinFET）的结构和方法，至少一个第一鳍结构和位于掩埋氧化物层上的至少一个第二鳍结构。 第一间隔件与第一翅片结构相邻，第二间隔件邻近第二翅片结构。 当与由第二间隔物覆盖的第二鳍结构的部分相比时，第一间隔物覆盖第一鳍结构的较大部分。 具有较大间隔物的那些翅片将接收较小的半导体掺杂面积，并且具有较小间隔物的那些翅片将接收更大面积的半导体掺杂。 因此，由不同尺寸的间隔件引起的第一散热片和第二散热片之间的掺杂存在差异。 与第一鳍片相比，第一鳍片和第二鳍片之间的掺杂差异改变了第二鳍片的有效宽度。

公开(公告)号：US20070108537A1

公开(公告)日：2007-05-17

申请号：US11164216

申请日：2005-11-15

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

IPC分类号： H01L21/8244

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.

摘要翻译： 公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。 厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。 为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。

公开(公告)号：US20070108528A1

公开(公告)日：2007-05-17

申请号：US11164218

申请日：2005-11-15

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L29/785 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： Disclosed is an SRAM cell on an SOI, bulk or HOT wafer with two pass-gate n-FETs, two pull-up p-FETs and two pull-down n-FETs and the associated methods of making the SRAM cell. The pass-gate FETs and pull-down FETs are non-planar fully depleted finFETs or trigate FETs. The pull-down FETs comprise non-planar partially depleted three-gated FETs having a greater channel width and a greater gate length and, thus, a greater drive current relative to the pass-gate and pull-up FETs. Additionally, for optimal electron mobility and hole mobility, respectively, the channels of the n-FETs and p-FETs can comprise semiconductors with different crystalline orientations.

摘要翻译： 公开了具有两个通过栅极n-FET，两个上拉p-FET和两个下拉n-FET的SOI，体或HOT晶片上的SRAM单元以及制造SRAM单元的相关方法。 栅极FET和下拉FET是非平面完全耗尽的finFET或触发FET。 下拉式FET包括具有较大沟道宽度和较大栅极长度以及因此相对于栅极和上拉FET的较大驱动电流的非平面部分耗尽的三门式FET。 此外，为了分别实现最佳的电子迁移率和空穴迁移率，n-FET和p-FET的沟道可以包括具有不同结晶取向的半导体。

公开(公告)号：US20070085134A1

公开(公告)日：2007-04-19

申请号：US10596029

申请日：2003-12-08

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/792 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/1211 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit semiconductor memory device (100) has a first dielectric layer (116) characterized as the BOX layer absent from a portion (130) of the substrate (112) under the gate of a storage transistor to increase the gate-to-substrate capacitance and thereby reduce the soft error rate. A second dielectric layer (132) having a property different from the first dielectric layer at least partly covers that portion (130) of the substrate. The device may be a FinFET device including a fin (122) and a gate dielectric layer (124, 126) between the gate and the fin, with the second dielectric layer having less leakage than the gate dielectric layer.

摘要翻译： 集成电路半导体存储器件（100）具有第一介电层（116），其特征在于，在存储晶体管的栅极下方的衬底（112）的部分（130）中不存在BOX层，以增加栅极到衬底 电容，从而降低软错误率。 具有不同于第一电介质层的性质的第二电介质层（132）至少部分地覆盖衬底的该部分（130）。 器件可以是FinFET器件，其包括在栅极和鳍之间的鳍（122）和栅极电介质层（124,126），其中第二介电层具有比栅极电介质层更少的泄漏。

公开(公告)号：US20060286778A1

公开(公告)日：2006-12-21

申请号：US11160365

申请日：2005-06-21

申请人： Brent Anderson ,  John Ellis-Monaghan ,  Alain Loiseau ,  Kirk Peterson

发明人： Brent Anderson ,  John Ellis-Monaghan ,  Alain Loiseau ,  Kirk Peterson

IPC分类号： H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/8252

摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.

摘要翻译： 公开了制造双取向晶片的方法。 在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。 沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。 形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。 另外的隔离结构形成在沟槽内和半导体层内的硅材料内。 对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。 所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

公开(公告)号：US20060267111A1

公开(公告)日：2006-11-30

申请号：US11436480

申请日：2006-05-18

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.

摘要翻译： 一种半导体结构及其形成方法。 该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。 该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等 ）。 前门的宽度大于后门的宽度。 前门和S / D区之间的电容小于后门和S / D区之间的电容。 前门和S / D区之间的距离大于后门和S / D区之间的距离。