公开(公告)号：US20060215303A1

公开(公告)日：2006-09-28

申请号：US11324227

申请日：2006-01-04

申请人： Ji-Young Kim

发明人： Ji-Young Kim

IPC分类号： G11B19/02 ,  G11B21/02

CPC分类号： G11B5/54 ,  G11B5/5582 ,  G11B19/04 ,  G11B19/08

摘要： A portable wireless communication terminal includes a sensor to detect a movement of the portable wireless communication terminal and output a first signal based on an acceleration of the movement and a second signal based on a velocity of the movement and a controller to control a hard disk drive (HDD) in response to both the first and second signals.

摘要翻译： 便携式无线通信终端包括：传感器，用于检测便携式无线通信终端的移动，并基于移动的加速度输出第一信号;基于移动速度输出第二信号;以及控制器，用于控制硬盘驱动器 （HDD）响应于第一和第二信号。

公开(公告)号：US20060170459A1

公开(公告)日：2006-08-03

申请号：US11340458

申请日：2006-01-27

申请人： Jong-Shin Shin ,  Ji-Young Kim ,  Myoung-Bo Kwak ,  Il-Won Seo ,  Chi-Won Kim ,  Hyun-Goo Kim ,  Jae-Hyun Park

发明人： Jong-Shin Shin ,  Ji-Young Kim ,  Myoung-Bo Kwak ,  Il-Won Seo ,  Chi-Won Kim ,  Hyun-Goo Kim ,  Jae-Hyun Park

IPC分类号： H03K19/094

CPC分类号： H03K17/693

摘要： A multiplexer and methods thereof. In an example, the multiplexer may receive a first periodic signal with a first active duration and a second periodic signal with a second active duration, the first and second active durations not overlapping. The multiplexer may transition statuses of first and second transmission gates based on the first and second periodic signals, respectively, such that each of the first and second transmission gates are set to the same status during at least one time period (e.g., between the first and second active durations where both the first and second periodic signals are inactive). In a further example, the example multiplexer may include first and second transmission gates receiving first and second input signals which may be controlled by the first and second control signals.

摘要翻译： 多路复用器及其方法。 在一个示例中，多路复用器可以接收具有第一有效持续时间的第一周期性信号和具有第二有效持续时间的第二周期信号，第一和第二有效持续时间不重叠。 复用器可以分别基于第一和第二周期信号转换第一和第二传输门的状态，使得第一和第二传输门中的每一个在至少一个时间段内（例如，在第一和第二周期信号之间）被设置为相同的状态 和第二有效持续时间，其中第一和第二周期信号都不起作用）。 在另一示例中，示例多路复用器可以包括接收可由第一和第二控制信号控制的第一和第二输入信号的第一和第二传输门。

公开(公告)号：US20060008994A1

公开(公告)日：2006-01-12

申请号：US11229202

申请日：2005-09-15

申请人： Nak-Jin Son ,  Ji-Young Kim

发明人： Nak-Jin Son ,  Ji-Young Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/78

摘要： A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

摘要翻译： 公开了一种半导体器件及其制造方法。 在半导体衬底的有源区中形成沟槽。 掺杂层形成在沟槽的内壁上。 沟槽填充有第一半导体层。 在第一半导体层和基板上形成栅极绝缘层。 在栅极绝缘层上形成两个栅电极，使得沟槽位于两个栅电极之间。 在每个栅电极的两侧的基板中形成第一和第二杂质区。 由于掺杂层局部地形成在沟槽区域中，源极和漏极区域与重掺杂层完全分离，以削弱PN结的电场，从而改善了源极和漏极之间的刷新并防止穿透。

公开(公告)号：US20060001107A1

公开(公告)日：2006-01-05

申请号：US11100596

申请日：2005-04-07

申请人： Ji-Young Kim ,  Chang-Sub Lee ,  Sang-Jun Park ,  Hyo-June Kim

发明人： Ji-Young Kim ,  Chang-Sub Lee ,  Sang-Jun Park ,  Hyo-June Kim

IPC分类号： H01L27/108

CPC分类号： H01L21/76232 ,  H01L27/10876 ,  H01L29/66621

摘要： A transistor including an active region and methods thereof. The active region may include corners with at least one of a rectangular, curved or rounded shape. The methods may include isotropically etching at least a portion of the active region such that the portion includes a desired shape.

公开(公告)号：US06921919B2

公开(公告)日：2005-07-26

申请号：US10633048

申请日：2003-07-31

申请人： Ji-Young Kim ,  Sang-Yong Kim

发明人： Ji-Young Kim ,  Sang-Yong Kim

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L23/31 ,  H01L29/04 ,  H01L31/036

CPC分类号： H01L29/6656 ,  H01L21/823437 ,  H01L21/823468 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device protecting the ends of a gate line and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate, a gate line crossing over the semiconductor substrate, and a protecting pattern covering ends of the gate line. According to the method, a gate line is formed at a semiconductor substrate. A spacer is formed to cover sidewalls of the gate line. A protecting pattern is formed to cover the ends of the gate line. The protecting pattern may be formed of silicon nitride or silicon oxide. Since the protecting pattern protects ends of a gate line, it is possible to prevent gate electrodes from being damaged by a cleaning solution such as SC1 in a subsequent process.

摘要翻译： 公开了保护栅极线的端部的半导体器件及其形成方法。 半导体器件包括半导体衬底，跨越半导体衬底的栅极线和覆盖栅极线的端部的保护图案。 根据该方法，在半导体衬底上形成栅极线。 形成间隔件以覆盖栅极线的侧壁。 形成保护图案以覆盖栅极线的端部。 保护图案可以由氮化硅或氧化硅形成。 由于保护图案保护栅极线的端部，因此可以防止在随后的工艺中栅电极被诸如SC1的清洁溶液损坏。

公开(公告)号：US20050064640A1

公开(公告)日：2005-03-24

申请号：US10971353

申请日：2004-10-22

申请人： Yong-jik Park ,  Ji-Young Kim

发明人： Yong-jik Park ,  Ji-Young Kim

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/66651 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/66575

摘要： Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes an isolation insulating film, an epitaxial silicon layer, a junction blocking insulating film, a gate stack, and source and drain junctions. The isolation insulating film is formed on a semiconductor substrate to define an active area. The epitaxial silicon layer is formed in the active area of the semiconductor substrate and surrounded by the isolation insulating film. The junction blocking insulating film is formed in the epitaxial silicon layer. The gate stack is formed over the epitaxial silicon layer so that the junction blocking insulating film is buried under approximately the center of the gate stack. The source and drain junctions are formed adjacent the sidewalls of the gate stack. Accordingly, a short circuit between source/drain junctions in a bulk area caused by the unwanted diffusion of the junctions can be prevented.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括隔离绝缘膜，外延硅层，接合阻挡绝缘膜，栅极堆叠以及源极和漏极结。 隔离绝缘膜形成在半导体衬底上以限定有源区。 外延硅层形成在半导体衬底的有源区中并被隔离绝缘膜包围。 接合阻挡绝缘膜形成在外延硅层中。 栅极堆叠形成在外延硅层上，使得接合阻挡绝缘膜被埋在栅堆叠的大约中心附近。 源极和漏极结邻近栅堆叠的侧壁形成。 因此，可以防止由接合点的不想要的扩散引起的在大块区域中的源极/漏极结之间的短路。

公开(公告)号：US20050014338A1

公开(公告)日：2005-01-20

申请号：US10649262

申请日：2003-08-26

申请人： Ji-Young Kim ,  Hyoung-Sub Kim

发明人： Ji-Young Kim ,  Hyoung-Sub Kim

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L29/80

CPC分类号： H01L21/823456 ,  H01L21/823437 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

摘要： Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

公开(公告)号：US09422729B2

公开(公告)日：2016-08-23

申请号：US13978498

申请日：2011-06-13

申请人： Hyun-Jong Kwon ,  Ji-Young Kim ,  Ki-Bong Park ,  Chang-Won Kang ,  Jun-Hyuk Kwon ,  Sang-Sun Park ,  Jang-Ki Kim ,  Gyeong-Min Lee ,  Cheng-Zhe Huang

发明人： Hyun-Jong Kwon ,  Ji-Young Kim ,  Ki-Bong Park ,  Chang-Won Kang ,  Jun-Hyuk Kwon ,  Sang-Sun Park ,  Jang-Ki Kim ,  Gyeong-Min Lee ,  Cheng-Zhe Huang

IPC分类号： B32B5/16 ,  E04F15/12 ,  B32B27/36 ,  B32B7/12 ,  B32B27/12 ,  B32B27/18 ,  E04F15/10

CPC分类号： E04F15/12 ,  B32B5/16 ,  B32B7/12 ,  B32B27/12 ,  B32B27/18 ,  B32B27/36 ,  B32B2255/10 ,  B32B2255/26 ,  B32B2307/412 ,  B32B2471/00 ,  E04F15/105 ,  E04F15/107 ,  Y10T428/2481 ,  Y10T428/24876 ,  Y10T428/24893

摘要： Disclosed herein is a chip inlaid flooring material using a PLA resin. The chip inlaid flooring material includes a chip inlaid layer, a dimension stabilizing layer, and a base layer, from the top of the flooring material, wherein at least one of the chip inlaid layer and the base layer includes polylactic acid (PLA) resin as a binder.

摘要翻译： 本文公开了使用PLA树脂的镶嵌镶嵌地板材料。 镶嵌地板材料的镶嵌材料包括从地板材料顶部的镶嵌层，尺寸稳定层和基层，其中，所述芯片镶嵌层和基层中的至少一个包括聚乳酸（PLA）树脂作为 粘合剂

公开(公告)号：US09048329B2

公开(公告)日：2015-06-02

申请号：US14024737

申请日：2013-09-12

申请人： Ji-Young Kim ,  Kang L. Wang ,  Yong-Jik Park ,  Jeong-Hee Han ,  Augustin Jinwoo Hong

发明人： Ji-Young Kim ,  Kang L. Wang ,  Yong-Jik Park ,  Jeong-Hee Han ,  Augustin Jinwoo Hong

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L29/7926 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.

摘要翻译： 集成电路器件包括其中具有可独立控制的栅电极的垂直堆叠的晶体管阵列。 提供第一半导体沟道区，其在独立可控栅电极的垂直叠层的第一侧壁上延伸。 还提供了第一电绝缘层，其在第一半导体沟道区域和独立可控栅电极的垂直叠层的第一侧壁之间延伸。 源极和漏极区分别电耦合到第一半导体沟道区的第一和第二端。

公开(公告)号：US09029857B2

公开(公告)日：2015-05-12

申请号：US13096330

申请日：2011-04-28

申请人： Jin-Goo Kang ,  Young-In Hwang ,  Ji-Young Kim ,  Hyo-Seok Kim

发明人： Jin-Goo Kang ,  Young-In Hwang ,  Ji-Young Kim ,  Hyo-Seok Kim

IPC分类号： H01L27/32

CPC分类号： H01L27/3223

摘要： An organic light-emitting display device includes a substrate including a rectangular light-emitting area and a circuit area, the circuit area including a thin film transistor, the light-emitting area including an electroluminescent layer produced by a solution deposition process, the light-emitting area being bounded by a first major side, a second major side, a first minor side and a second minor side, the first major side being opposite from and parallel to a second major side, each of these sides having wiring or dummies arranged thereat, and a pixel defining layer arranged on the wirings and on the dummies. In order to produce a uniform thickness electroluminescent layer via a solution deposition process, top surfaces of the pixel defining layer on each of the wirings and dummies that border the light emitting area are arranged in a same plane that is parallel to the substrate.

摘要翻译： 有机发光显示装置包括具有矩形发光区域和电路区域的基板，所述电路区域包括薄膜晶体管，所述发光区域包括通过溶液沉积工艺制造的电致发光层， 发光区域由第一主侧面，第二主侧面，第一次侧面和第二次要侧面限定，第一主侧面与第二主侧面相对并平行，其中每个侧面布置有布线或虚拟物 以及布置在布线和虚拟物上的像素限定层。 为了通过溶液沉积工艺制造出均匀的厚度的电致发光层，每个布线上的像素限定层的顶表面和与发光区域相邻的虚拟体被布置在与衬底平行的同一平面中。