公开(公告)号：US07952413B2

公开(公告)日：2011-05-31

申请号：US12795132

申请日：2010-06-07

申请人： Dae-Han Kwon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G06F1/06

CPC分类号： G06F1/06

摘要： A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.

摘要翻译： 一种时钟发生电路，包括：脉冲发生单元，用于基于参考时钟产生多个脉冲信号;每个脉冲信号具有相同的周期;相邻脉冲信号之间的相位差是第一相位差; 以及多相时钟发生单元，用于生成多个多相时钟，相邻的多相时钟之间的相位差等于脉冲信号对的脉冲信号之间的第二相位差，基于多个单位 接收脉冲信号对的相位时钟发生单元。

公开(公告)号：US07952388B1

公开(公告)日：2011-05-31

申请号：US12648477

申请日：2009-12-29

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/017509 ,  H03K19/018514 ,  H03K19/018528

摘要： A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than the first voltage level, and a CML clock transfer buffering unit configured to use a second power supply voltage as a power supply voltage and buffer the CML clock, which is transferred from the swing level shifting unit and swings around the second voltage level.

摘要翻译： 一种半导体器件包括：摆动电平移位单元，被配置为使用第一电源电压作为电源电压，接收围绕第一电压电平摆动的CML时钟，并将CML时钟的摆幅参考电压电平移位到第二电压电平 低于第一电压电平的CML时钟传送缓冲单元，以及CML时钟传送缓冲单元，被配置为使用第二电源电压作为电源电压，并缓冲从摆动电平移位单元传送的CML时钟，并围绕第二电压电平摆动。

公开(公告)号：US07796064B2

公开(公告)日：2010-09-14

申请号：US12215772

申请日：2008-06-30

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

摘要翻译： 并行转换器包括：数据输入单元，被配置为通过使用具有不同相位的多个时钟信号来接收多个并行数据;以及并行到串行转换单元，被配置为顺序地选择和输出 数据输入单元通过使用与数据输入单元中使用的多个时钟信号具有预定相位差的多个时钟信号。

公开(公告)号：US20100007375A1

公开(公告)日：2010-01-14

申请号：US12327294

申请日：2008-12-03

申请人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K17/16

CPC分类号： H03K19/018585 ,  H04L25/0298

摘要： A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal.

摘要翻译： 终端电阻电路包括控制信号发生器，用于产生当校准码具有预定值时其逻辑值改变的控制信号，响应于校准码分别导通/关断的多个并联电阻器，以及电阻值 改变单元，用于响应于控制信号改变终端电阻电路的总电阻值。

公开(公告)号：US20090279378A1

公开(公告)日：2009-11-12

申请号：US12164797

申请日：2008-06-30

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

IPC分类号： G11C8/18

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers.

摘要翻译： 一种半导体存储器件，包括用于接收源时钟并将产生的时钟提供给多个时钟传输线的时钟输入; 多个时钟放大器，每个时钟放大器响应于列使能信号放大加载在所述多个时钟传输线中的一个上的相应的生成时钟; 以及用于响应于由多个时钟放大器输出的放大时钟而输入/输出多个数据的数据输入/输出。

公开(公告)号：US20090175116A1

公开(公告)日：2009-07-09

申请号：US12165045

申请日：2008-06-30

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kum Yoon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kum Yoon

IPC分类号： G11C8/18 ,  H03L7/06

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  H03K2005/00208 ,  H03L7/0805 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/24

摘要： A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

摘要翻译： 一种具有时钟同步电路的半导体存储器件，其能够执行期望的相位/频率锁定操作，而没有抖动峰化现象和使用注入锁定的振荡控制电压信号的模式抖动。 该装置包括锁相环，其检测反馈时钟信号和参考时钟信号之间的相位/频率差，以产生对应于检测到的相位/频率差的振荡控制电压信号，并产生对应于 振荡控制电压信号。 注入锁定振荡单元响应于振荡控制电压信号建立自由运行频率，并产生与参考时钟信号同步的内部时钟信号。

公开(公告)号：US08542044B2

公开(公告)日：2013-09-24

申请号：US13334241

申请日：2011-12-22

申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

公开(公告)号：US20090058464A1

公开(公告)日：2009-03-05

申请号：US12005443

申请日：2007-12-26

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/018521 ,  H03K19/0948

摘要： A current mode logic (CML)-complementary metal oxide semiconductor (CMOS) converter prevents change of a duty ratio to stably operate during an operation for converting a CML level signal into a CMOS level signal. The CML-CMOS converter includes a reference level shifting unit configured to receive a CML signal swinging about a first reference level to shift a swing reference level to a second reference level; and an amplifying unit configured to amplify an output signal of the reference level shifting unit to output the amplified signal as a CMOS signal.

摘要翻译： 电流模式逻辑（CML） - 互补金属氧化物半导体（CMOS）转换器在用于将CML电平信号转换为CMOS电平信号的操作期间防止占空比的变化以稳定地操作。 CML-CMOS转换器包括参考电平移位单元，被配置为接收围绕第一参考电平摆动的CML信号，以将摆幅参考电平移位到第二参考电平; 以及放大单元，被配置为放大参考电平移位单元的输出信号以输出放大的信号作为CMOS信号。

公开(公告)号：US20130099838A1

公开(公告)日：2013-04-25

申请号：US13334241

申请日：2011-12-22

申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC分类号： H03L7/095

CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

公开(公告)号：US07768307B2

公开(公告)日：2010-08-03

申请号：US12005443

申请日：2007-12-26

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K19/0948

摘要： A current mode logic (CML)-complementary metal oxide semiconductor (CMOS) converter prevents change of a duty ratio to stably operate during an operation for converting a CML level signal into a CMOS level signal. The CML-CMOS converter includes a reference level shifting unit configured to receive a CML signal swinging about a first reference level to shift a swing reference level to a second reference level; and an amplifying unit configured to amplify an output signal of the reference level shifting unit to output the amplified signal as a CMOS signal.

摘要翻译： 电流模式逻辑（CML） - 互补金属氧化物半导体（CMOS）转换器在用于将CML电平信号转换为CMOS电平信号的操作期间防止占空比的变化以稳定地操作。 CML-CMOS转换器包括参考电平移位单元，被配置为接收围绕第一参考电平摆动的CML信号，以将摆幅参考电平移位到第二参考电平; 以及放大单元，被配置为放大参考电平移位单元的输出信号以输出放大的信号作为CMOS信号。