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公开(公告)号：US06608630B1
公开(公告)日：2003-08-19
申请号：US09437325
申请日：1999-11-09
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G500
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形集成电路芯片。 图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。 该芯片包括一个显示引擎，用于处理组织为Windows的图形图像。 该系统包括用于接收图形内容的多个行缓冲器。 将图形内容通过将图形内容与行缓冲存储器的现有内容进行混合直到所有行的所有图形表面都被合成，来合成到多个行缓冲器的每一行中。
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公开(公告)号：US06529935B1
公开(公告)日：2003-03-04
申请号：US09712736
申请日：2000-11-14
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F946
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形显示系统集成电路。 图形显示系统处理模拟视频输入，数字视频输入和图形输入。 该系统包含由图形系统，CPU和其他外围设备共享的统一存储器架构。 统一存储器架构使用实时调度来服务任务。 关键瞬时分析用于查找不影响实时任务的内存需求的内存使用计划，同时根据需要为非实时任务进行服务。
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公开(公告)号：US06380945B1
公开(公告)日：2002-04-30
申请号：US09437206
申请日：1999-11-09
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G506
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The display engine processes graphics images formatted in any one of a plurality of formats including a color look up table (CLUT) format. A color look-up (CLUT) table loading mechanism preferably facilitates the transfer of real-time CLUT table data during graphics composition. The loading mechanism may be triggered by a window descriptor that contains a color look-up table load command.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形集成电路芯片。 图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。 该芯片包括一个显示引擎，用于处理组织为Windows的图形图像。 显示引擎处理以包括彩色查找表（CLUT）格式的多种格式中的任何一种格式化的图形图像。 彩色查找（CLUT）表加载机制优选地有助于在图形组合期间传送实时CLUT表数据。 加载机制可以由包含颜色查找表加载命令的窗口描述符来触发。
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54.发明授权公开(公告)号：US08659608B2
公开(公告)日：2014-02-25
申请号：US12235156
申请日：2008-09-22
IPC分类号： G06F13/14
CPC分类号： G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2300/0408 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/0428 , G09G2340/06 , G09G2340/10 , G09G2340/12 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N9/45 , H04N9/641 , H04N9/642 , H04N9/75 , H04N9/78 , H04N11/143 , H04N11/20 , H04N19/112 , H04N19/16 , H04N19/186 , H04N19/20 , H04N19/27 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N19/80 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/4438 , H04N21/47
摘要： A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system as well as external peripheral devices. The system bridge controller is capable of performing format conversion between big-endian data and little-endian data. The system bridge controller includes a PCI bridge to interface with PCI devices, an I/O bus bridge to interface with I/O devices such as RAM, ROM, flash memory and 68000-compatible peripheral devices, and a CPU interface block to interface the CPU to video processing devices on the integrated circuit chip such as an MPEG video decoder.
摘要翻译： 集成电路芯片上的视频和图形系统包括集成系统桥接控制器，用于将CPU与系统内部的设备以及外部外围设备进行接口。 系统桥控制器能够执行大端数据和小端数据之间的格式转换。 系统桥控制器包括与PCI设备连接的PCI桥接器，与I / O设备（如RAM，ROM，闪存和68000兼容外围设备）进行接口的I / O总线桥接器，以及接口 CPU到视频处理设备上的集成电路芯片如MPEG视频解码器。
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公开(公告)号：US20110292074A1
公开(公告)日：2011-12-01
申请号：US12953168
申请日：2010-11-23
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G5/00
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.
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公开(公告)号：US20110273476A1
公开(公告)日：2011-11-10
申请号：US13181258
申请日：2011-07-12
IPC分类号： G09G5/00
CPC分类号： H04N5/44508 , H04N21/42653
摘要： Herein described is a method and system of displaying low resolution graphics onto a high resolution display. The low resolution graphics may be displayed using one or more displayable maps or surfaces, each of which is defined by way of one or more parameters. The display may comprise a monitor, television set, or set top box, capable of displaying at a particular resolution. In one or more representative embodiments, the various aspects of the invention permit scaling the low resolution graphics onto the high resolution display by way of using the one or more displayable maps or surfaces such that the graphics data is properly displayed on the higher resolution display.
摘要翻译： 这里描述的是在低分辨率显示器上显示低分辨率图形的方法和系统。 可以使用一个或多个可显示的地图或表面来显示低分辨率图形，每个地图或表面通过一个或多个参数来定义。 显示器可以包括能够以特定分辨率显示的监视器，电视机或机顶盒。 在一个或多个代表性实施例中，本发明的各个方面允许通过使用一个或多个可显示地图或表面将低分辨率图形缩放到高分辨率显示器上，使得图形数据被正确显示在较高分辨率显示器上。
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公开(公告)号：US08022966B2
公开(公告)日：2011-09-20
申请号：US12650361
申请日：2009-12-30
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar Radhakrishnan
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar Radhakrishnan
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US07920151B2
公开(公告)日：2011-04-05
申请号：US12472235
申请日：2009-05-26
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A video processing device may comprise one or more processors and/or circuits for use in a video processing device, in which the one or more processors and/or circuits may comprise a video scaler, a memory, a scaler engine, a clock selection circuit. The one or more processors and/or circuits are operable to receive a video image and select a video input clock or a display output clock for upscaling the received video image, or select the video input clock or the display output clock for downscaling the received video image based on a determination of whether the video image is to be downscaled or upscaled. The one or more circuits may be operable to downscale the received video image to generate a first scaled video image, and/or upscale the received video image to generate a second scaled video image, based on the selection.
摘要翻译： 视频处理设备可以包括用于视频处理设备中的一个或多个处理器和/或电路，其中一个或多个处理器和/或电路可以包括视频缩放器，存储器，缩放器引擎，时钟选择电路 。 所述一个或多个处理器和/或电路可操作以接收视频图像并选择视频输入时钟或显示输出时钟以升高所接收的视频图像，或者选择视频输入时钟或显示输出时钟以缩小所接收的视频 基于视频图像是否被缩小或放大的确定的图像。 所述一个或多个电路可操作以基于所述选择来降低所接收的视频图像以生成第一缩放视频图像，和/或升高所接收的视频图像以生成第二缩放视频图像。
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59.发明申请GRAPHICS DISPLAY SYSTEM WITH ANTI-FLUTTER FILTERING AND VERTICAL SCALING FEATURE 审中-公开具有防过滤和垂直缩放特征的图形显示系统公开(公告)号：US20100171762A1
公开(公告)日：2010-07-08
申请号：US12494909
申请日：2009-06-30
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G5/00
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形集成电路芯片。 图形芯片处理模拟视频输入，数字视频输入和图形输入。 该芯片包括单个多相滤波器，其优选地提供图像的防颤音滤波和缩放。 防颤音滤波可能有助于减少由于电视显示器的隔行特性引起的显示闪烁。 图形的缩放可以用于将图形的正方形像素长宽比转换为视频的正常矩形像素长宽比。
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公开(公告)号：US07746354B2
公开(公告)日：2010-06-29
申请号：US11617468
申请日：2006-12-28
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The system may use anti-aliased text and graphics to provide high quality display of graphical elements, or glyphs, which represent an image of a character of text or graphics, on television and other displays. The graphical elements may be superimposed over live video or arbitrary graphics imagery.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形集成电路芯片。 图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。 系统可以使用反锯齿的文本和图形来提供在电视和其他显示器上表示文本或图形的图像的图形元素或字形的高质量显示。 图形元素可以叠加在实时视频或任意图形图像上。
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