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公开(公告)号：US08022966B2
公开(公告)日：2011-09-20
申请号：US12650361
申请日：2009-12-30
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar Radhakrishnan
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar Radhakrishnan
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US06853385B1
公开(公告)日：2005-02-08
申请号：US09641374
申请日：2000-08-18
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
IPC分类号： G06T9/00 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/395 , G09G5/397 , G09G5/42 , H04N5/14 , H04N5/44 , H04N5/445 , H04N5/45 , H04N5/46 , H04N7/01 , H04N9/45 , H04N9/64 , H04N11/14 , H04N11/20 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/81 , H04L12/28 , H04N11/00 , H04N11/22
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
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公开(公告)号：US20100103195A1
公开(公告)日：2010-04-29
申请号：US12650361
申请日：2009-12-30
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US07667715B2
公开(公告)日：2010-02-23
申请号：US11498595
申请日：2006-08-03
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US07110006B2
公开(公告)日：2006-09-19
申请号：US10997652
申请日：2004-11-23
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
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公开(公告)号：US20060268012A1
公开(公告)日：2006-11-30
申请号：US11498595
申请日：2006-08-03
申请人： Alexander MacInnis , Chengfuh Tang , Xiaodong Xie , Greg Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander MacInnis , Chengfuh Tang , Xiaodong Xie , Greg Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
IPC分类号： G09G5/00
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US20050122335A1
公开(公告)日：2005-06-09
申请号：US10997652
申请日：2004-11-23
申请人： Alexander MacInnis , Chengfuh Tang , Xiaodong Xie , Greg Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander MacInnis , Chengfuh Tang , Xiaodong Xie , Greg Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
IPC分类号： G06T9/00 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/395 , G09G5/397 , G09G5/42 , H04N5/14 , H04N5/44 , H04N5/445 , H04N5/45 , H04N5/46 , H04N7/01 , H04N9/45 , H04N9/64 , H04N11/14 , H04N11/20 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/81 , G06F13/14
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US20120147974A1
公开(公告)日：2012-06-14
申请号：US13160461
申请日：2011-06-14
申请人： David A. BAER , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klingler , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
发明人： David A. BAER , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klingler , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
IPC分类号： H04N7/26
CPC分类号： H04N21/426 , H04N5/4401 , H04N5/44504 , H04N5/46 , H04N7/035 , H04N21/4263 , H04N21/4305 , H04N2005/91364
摘要： A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.
摘要翻译： 公开了一种提供用于在单个集成电路芯片上提供电视功能的成本有效方法的芯片上的电视（TVOC）系统。 TVOC包括以各种输入和输出格式接收和显示电视信号所必需的功能。 TVOC可用于有线和卫星电视的机顶盒，或直接在电视机内使用。 所提供的所有功能可以在单个集成电路上提供。 TVOC包括数据传输模块，IF解调器，数字音频引擎，模拟音频引擎，数字视频引擎和模拟视频引擎。 TVOC还包括三套接口，包括输出接口，控制接口和辅助接口。 其他特征和实施例提供增强的功能和提高的效率。
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公开(公告)号：US07489362B2
公开(公告)日：2009-02-10
申请号：US10791686
申请日：2004-03-03
申请人： David A. Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klingler , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
发明人： David A. Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klingler , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
CPC分类号： H04N21/426 , H04N5/4401 , H04N5/44504 , H04N5/46 , H04N7/035 , H04N21/4263 , H04N21/4305 , H04N2005/91364
摘要： A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.
摘要翻译： 公开了一种提供用于在单个集成电路芯片上提供电视功能的成本有效方法的芯片上的电视（TVOC）系统。 TVOC包括以各种输入和输出格式接收和显示电视信号所必需的功能。 TVOC可用于有线和卫星电视的机顶盒，或直接在电视机内使用。 所提供的所有功能可以在单个集成电路上提供。 TVOC包括数据传输模块，IF解调器，数字音频引擎，模拟音频引擎，数字视频引擎和模拟视频引擎。 TVOC还包括三套接口，包括输出接口，控制接口和辅助接口。 其他特征和实施例提供增强的功能和提高的效率。
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公开(公告)号：US07961255B2
公开(公告)日：2011-06-14
申请号：US12367425
申请日：2009-02-06
申请人： David A. Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klinger , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
发明人： David A. Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klinger , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
CPC分类号： H04N21/426 , H04N5/4401 , H04N5/44504 , H04N5/46 , H04N7/035 , H04N21/4263 , H04N21/4305 , H04N2005/91364
摘要： A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.
摘要翻译： 公开了一种提供用于在单个集成电路芯片上提供电视功能的成本有效方法的芯片上的电视（TVOC）系统。 TVOC包括以各种输入和输出格式接收和显示电视信号所必需的功能。 TVOC可用于有线和卫星电视的机顶盒，或直接在电视机内使用。 所提供的所有功能可以在单个集成电路上提供。 TVOC包括数据传输模块，IF解调器，数字音频引擎，模拟音频引擎，数字视频引擎和模拟视频引擎。 TVOC还包括三套接口，包括输出接口，控制接口和辅助接口。 其他特征和实施例提供增强的功能和提高的效率。
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