公开(公告)号：US20110076782A1

公开(公告)日：2011-03-31

申请号：US12888394

申请日：2010-09-22

申请人： Tara L. Awezec ,  Dylan Joseph Boday ,  Lee Curtis Randall ,  Stephen Leonard Schwartz ,  Anna W. Topol ,  Daniel James Winarski

发明人： Tara L. Awezec ,  Dylan Joseph Boday ,  Lee Curtis Randall ,  Stephen Leonard Schwartz ,  Anna W. Topol ,  Daniel James Winarski

IPC分类号： G01N33/53 ,  B01J19/00

CPC分类号： G01N33/54346 ,  B82Y15/00 ,  G01N33/54326 ,  G01N33/54333

摘要： Embodiments of the invention relate to magnetizing and detecting nanoparticle-labeled antigens on biosample tracks deposited on a tape media. An aspect of the invention comprises apparatus and methods for labeling antigens with demagnetized nanoparticles, magnetizing the nanoparticles with an electromagnetic write head, and detecting the antigens via the magnetized nanoparticles by reading the tape media with a read sensor in a read-after-write operation. The write head and read sensor are part of a head-module of magnetic tape drive. Target antigens are attached to the biosample tracks by antibodies. Nanoparticles of differing magnetic properties may be selectively paired with antibodies associated with different antigens to allow multiple antigens to be detected upon a single scan by the read sensor.

摘要翻译： 本发明的实施方案涉及在沉积在带介质上的生物样品轨道上磁化和检测纳米颗粒标记的抗原。 本发明的一个方面包括用去磁纳米颗粒标记抗原的装置和方法，用电磁写头磁化纳米颗粒，并通过在读写操作中用读取传感器读取磁带介质，通过磁化纳米颗粒检测抗原 。 写头和读取传感器是磁带驱动器的头模块的一部分。 靶抗原通过抗体连接到生物样品轨道上。 具有不同磁性的纳米颗粒可以与与不同抗原相关的抗体选择性配对，以允许通过读取传感器进行单次扫描来检测多个抗原。

公开(公告)号：US07847357B2

公开(公告)日：2010-12-07

申请号：US12556261

申请日：2009-09-09

申请人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

发明人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

IPC分类号： H01L27/092 ,  H01L21/31 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.

摘要翻译： 本发明涉及具有间隙填充物的具有间隙双重应力的互补金属氧化物半导体（CMOS）器件。 具体地，本发明的每个CMOS器件包括至少一个n沟道场效应晶体管（n-FET）和至少一个p沟道场效应晶体管（p-FET）。 拉伸应力介电层覆盖n-FET，并且压应力介电层覆盖p-FET。 间隙位于拉伸和压应力介电层之间，并填充有介电填料。 在本发明的一个具体实施方案中，拉伸和压缩应力介电层都被基本上没有应力的介电填料材料层覆盖。 在本发明的替代实施例中，电介质填充材料仅存在于拉伸和压缩应力介电层之间的间隙中。

公开(公告)号：US20100255262A1

公开(公告)日：2010-10-07

申请号：US11532599

申请日：2006-09-18

申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Sampath Purushothaman ,  David L. Rath ,  Anna W. Topol ,  Cornelia K. Tsang

发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Sampath Purushothaman ,  David L. Rath ,  Anna W. Topol ,  Cornelia K. Tsang

IPC分类号： B32B3/00 ,  B23K31/02

CPC分类号： H01L24/05 ,  B23K20/023 ,  B23K20/233 ,  B23K20/24 ,  B23K2101/42 ,  H01L24/03 ,  H01L24/08 ,  H01L24/12 ,  H01L24/80 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24545 ,  Y10T428/24612 ,  Y10T428/31678 ,  H01L2924/00012 ,  H01L2924/0001 ,  H01L2924/00

摘要： Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric is disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

摘要翻译： 公开了包括金属介电图案在衬底上的金属与在电介质上方凸起的金属的结合。 一种方法包括在其表面上提供具有金属 - 电介质图案的第一基板; 提供在其表面上具有金属 - 电介质图案的第二基板; 执行导致金属在电介质上方升高的过程; 清洗金属; 以及将所述第一基板接合到所述第二基板。 还公开了相关的结构。 凸起金属的结合提供了强大的粘合介质，以及良好的电气和热连接，能够创建具有增强功能的三维集成结构。

公开(公告)号：US07598540B2

公开(公告)日：2009-10-06

申请号：US11451869

申请日：2006-06-13

申请人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

发明人： Bruce B. Doris ,  Thomas W. Dyer ,  David R. Medeiros ,  Anna W. Topol

IPC分类号： H01L31/00 ,  H01L29/739

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.

摘要翻译： 本发明涉及具有间隙填充物的具有间隙双重应力的互补金属氧化物半导体（CMOS）器件。 具体地，本发明的每个CMOS器件包括至少一个n沟道场效应晶体管（n-FET）和至少一个p沟道场效应晶体管（p-FET）。 拉伸应力介电层覆盖n-FET，并且压应力介电层覆盖p-FET。 间隙位于拉伸和压应力介电层之间，并填充有介电填料。 在本发明的一个具体实施方案中，拉伸和压缩应力介电层都被基本上没有应力的介电填料材料层覆盖。 在本发明的替代实施例中，电介质填充材料仅存在于拉伸和压缩应力介电层之间的间隙中。

公开(公告)号：US20080268574A1

公开(公告)日：2008-10-30

申请号：US12035053

申请日：2008-02-21

申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC分类号： H01L21/58

CPC分类号： H01L25/50 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

摘要翻译： 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。