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51.发明授权Method, system and computer program product for sampling computer system performance data 失效方法，系统和计算机程序产品，用于对计算机系统性能数据进行采样公开(公告)号：US07870438B2
公开(公告)日：2011-01-11
申请号：US12031727
申请日：2008-02-15
申请人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, Jr.
发明人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, Jr.
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3476
摘要： A system, method and computer program product for sampling computer system performance data are provided. The system includes a sample buffer to store instrumentation data while capturing trace data in a trace array, where the instrumentation data enables measurement of computer system performance. The system further includes a sample interrupt generator to assert a sample interrupt indicating that the instrumentation data is available to read. The sample interrupt is asserted in response to storing the instrumentation data in the sample buffer.
摘要翻译： 提供了一种用于采样计算机系统性能数据的系统，方法和计算机程序产品。 该系统包括一个样本缓冲区，用于存储仪器数据，同时捕获跟踪阵列中的跟踪数据，其中仪器数据可以测量计算机系统性能。 该系统还包括一个样本中断发生器，用于断言一个样本中断，指示仪器数据可用于读取。 响应于将仪器数据存储在采样缓冲器中，取样中断被置位。
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52.发明申请PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT INCLUDING SPECIALIZED STORE QUEUE AND BUFFER DESIGN FOR SILENT STORE IMPLEMENTATION 有权处理器，方法和计算机程序产品，其中包括专门针对存储商店的特殊店铺和缓冲设计，公开(公告)号：US20090210655A1
公开(公告)日：2009-08-20
申请号：US12031998
申请日：2008-02-15
IPC分类号： G06F9/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826
摘要： A processor including an architecture for limiting store operations includes: a data input and a cache input as inputs to data merge logic; a merge buffer for providing an output to an old data buffer, holding a copy of a memory location and two way communication with a new data buffer; compare logic for receiving old data from the old data buffer and new data from the new data buffer and comparing if the old data matches the new data, and if there is a match determining an existence of a silent store; and store data control logic for limiting store operations while the silent store exists. A method and a computer program product are provided.
摘要翻译： 包括用于限制存储操作的架构的处理器包括：作为数据合并逻辑的输入的数据输入和高速缓存输入; 用于向旧数据缓冲器提供输出的合并缓冲器，保持存储器位置的副本和与新数据缓冲器的双向通信; 比较用于从旧数据缓冲器接收旧数据和来自新数据缓冲器的新数据的比较逻辑，并比较旧数据是否与新数据匹配，以及是否存在确定静默存储的存在的匹配; 并存储用于限制存储操作的数据控制逻辑，同时存在无声存储。 提供了一种方法和计算机程序产品。
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53.发明申请MICROPROCESSOR AND METHOD FOR DEFERRED STORE DATA FORWARDING FOR STORE BACKGROUND DATA IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS 有权微处理器和方法，用于存储存储数据的存储数据在没有存储器模型限制的系统中的背景数据公开(公告)号：US20090210632A1
公开(公告)日：2009-08-20
申请号：US12031858
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , David B. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , David B. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/30043
摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.
摘要翻译： 流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。
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54.发明申请SYSTEM, METHOD AND APPARATUS FOR ENHANCING RELIABILITY ON SCAN-INITIALIZED LATCHES AFFECTING FUNCTIONALITY 有权系统，方法和装置，用于增强影响功能的扫描初始化锁存器的可靠性公开(公告)号：US20090206872A1
公开(公告)日：2009-08-20
申请号：US12031730
申请日：2008-02-15
IPC分类号： H03K19/003
CPC分类号： H03K19/0033
摘要： A system, method, and apparatus for enhancing reliability on scan-initialized latches that affect functionality in a digital design are provided. The system includes a group of latches that affect functionality in the digital design based on state values of the latches, where the latches are scan initialized. The system also includes a disable allowance latch (DAL) allocated to the group of latches, where the DAL is a scan-initialized latch. The system further includes a gating function outputting the state value of at least one of the latches in the group to a functional block in the digital design in response to the DAL being in an enabled state and blocking the gating function output in response to the DAL being in a disabled state.
摘要翻译： 提供了一种用于提高影响数字设计中的功能的扫描初始化锁存器的可靠性的系统，方法和装置。 该系统包括一组锁存器，其基于锁存器的状态值影响数字设计中的功能，其中锁存器被扫描初始化。 该系统还包括分配给锁存器组的禁用允许锁存器（DAL），其中DAL是扫描初始化的锁存器。 该系统还包括选通功能，以响应于DAL处于使能状态，将组中的至少一个锁存器的状态值输出到数字设计中的功能块，并响应于DAL阻塞门控功能输出 处于残疾状态。
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55.发明申请SYSTEM AND METHOD FOR AVOIDING DEADLOCKS WHEN PERFORMING STORAGE UPDATES IN A MULTI-PROCESSOR ENVIRONMENT 有权在多处理器环境中执行存储更新时避免死锁的系统和方法公开(公告)号：US20090204763A1
公开(公告)日：2009-08-13
申请号：US12030627
申请日：2008-02-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F9/3824 , G06F9/3834 , G06F9/3867
摘要： A system and method for avoiding deadlocks when performing storage updates in a multi-processor environment. The system includes a processor having a local cache, a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be stored, and a mechanism for performing a method. The method includes setting the processor into a slow mode. A current instruction that includes a data store having one or more target lines is received. The current instruction is executed, with the executing including storing results associated with the data store into the temporary buffer. The store queue is prevented from rejecting an exclusive XI corresponding to the target lines of the current instruction. Each target line is acquired with a status of exclusive ownership, and the contents from the temporary buffer are written to each target line after instruction completion.
摘要翻译： 一种用于在多处理器环境中执行存储更新时避免死锁的系统和方法。 该系统包括具有本地高速缓存的处理器，具有临时缓冲器的存储队列，该临时缓冲器具有拒绝排他交叉询问（XI）的能力，同时询问的高速缓存行被独占地存储并被存储，以及用于执行方法的机制。 该方法包括将处理器设置为慢速模式。 接收包括具有一个或多个目标线的数据存储器的当前指令。 执行当前指令，执行包括将与数据存储相关联的结果存储到临时缓冲器中。 防止存储队列拒绝与当前指令的目标行相对应的排他的XI。 每个目标行被采集为具有独占所有权的状态，并且在指令完成之后将来自临时缓冲器的内容写入每个目标行。
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公开(公告)号：US20090187731A1
公开(公告)日：2009-07-23
申请号：US12353478
申请日：2009-01-14
CPC分类号： G06F12/1036 , G06F9/45558 , G06F12/0888 , G06F2009/45583
摘要： The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.
摘要翻译： 本发明涉及一种用于运行多级虚拟机的系统中的地址转换方法，该虚拟机包含分层组织的翻译后备缓冲器，其包括至少两个链接的分层子单元，第一子单元包括用于某些更高级地址转换的后备缓冲器 并且第二子单元包括用于一些较低级别地址转换级别的后备缓冲器，并且所述第二子单元被布置为将上级子单元的TLB索引地址信息作为标签信息存储在其较低级别的TLB结构中 包括以下步骤：在不同的虚拟机级上收集中间的地址转换结果; 并且将中间翻译结果缓冲到翻译后备缓冲器中。
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57.发明申请Multiprocessor electronic circuit including a plurality of processors and electronic data processing system 有权多处理器电子电路包括多个处理器和电子数据处理系统公开(公告)号：US20090113212A1
公开(公告)日：2009-04-30
申请号：US12248549
申请日：2008-10-09
IPC分类号： G06F21/00
CPC分类号： G06F21/72
摘要： A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.
摘要翻译： 公开了一种包括这种电路的多处理器电子电路和电子数据处理系统，用于降低具有加密功能的多处理器系统的功耗和芯片面积消耗。 在一个实施例中，多处理器电子电路包括多个处理器，包括多个输入/输出缓冲器对和两个加密引擎，密码引擎和哈希引擎以及相关控制逻辑的单个密码处理单元。
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公开(公告)号：US06745313B2
公开(公告)日：2004-06-01
申请号：US10042533
申请日：2002-01-09
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/1054 , G06F2212/6024
摘要： A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.
摘要翻译： 公开了一种用于在具有高速缓冲存储器和分支历史表的计算机系统中选择数据的方法，其中该方法包括预测对应于该数据的地址，在高速缓冲存储器中选择预测地址处的数据， 数据，将转换的地址与预测地址进行比较，如果它们不同，则在高速缓冲存储器中的翻译地址处重新选择数据，并将转换的地址附加到分支历史表。
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公开(公告)号：US08880805B2
公开(公告)日：2014-11-04
申请号：US13105235
申请日：2011-05-11
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译： 具有缓存子系统的计算机系统，其中降级请求由高速缓存子系统执行。 软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。 有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。 通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。 本发明还描述了提供此支持所需的硬件设计。
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公开(公告)号：US20120124292A1
公开(公告)日：2012-05-17
申请号：US13105235
申请日：2011-05-11
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译： 具有缓存子系统的计算机系统，其中降级请求由高速缓存子系统执行。 软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。 有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。 通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。 本发明还描述了提供此支持所需的硬件设计。
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