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70 条记录 (耗时 0.035 秒)

    Re-writable resistance-switching memory with balanced series stack
    52.
    发明授权
    Re-writable resistance-switching memory with balanced series stack 有权
    具有平衡串联堆叠的可重写电阻切换存储器

    公开(公告)号：US08693233B2

    公开(公告)日：2014-04-08

    申请号：US13363252

    申请日：2012-01-31

    申请人： Roy E Scheuerlein ,  Henry Chien ,  Zhida Lan ,  Yung-Tin Chen

    发明人： Roy E Scheuerlein ,  Henry Chien ,  Zhida Lan ,  Yung-Tin Chen

    IPC分类号： G11C11/00

    CPC分类号： H01L45/146 ,  G11C5/02 ,  G11C8/08 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/33 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145

    摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.

    摘要翻译： 可重写电阻切换存储单元包括串联的第一和第二电容器。 第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。 第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。 第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。 在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。 在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

    Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation
    57.
    发明申请
    Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation 有权
    具有扁平单元结构和空气间隙隔离的非易失性存储器

    公开(公告)号：US20110309430A1

    公开(公告)日：2011-12-22

    申请号：US13162550

    申请日：2011-06-16

    申请人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

    发明人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

    IPC分类号： H01L29/788 ,  H01L21/764

    CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649

    摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

    摘要翻译： 高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。 控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。 至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

    Methods of forming integrated circuit devices using composite spacer structures
    59.
    发明授权
    Methods of forming integrated circuit devices using composite spacer structures 有权
    使用复合间隔结构形成集成电路器件的方法

    公开(公告)号：US07795080B2

    公开(公告)日：2010-09-14

    申请号：US12014689

    申请日：2008-01-15

    申请人： Takashi Orimoto ,  George Matamis ,  James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  Henry Chien

    发明人： Takashi Orimoto ,  George Matamis ,  James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  Henry Chien

    IPC分类号： H01L21/82

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

    摘要： Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.

    摘要翻译： 使用复合间隔物形成工艺提供制造集成电路器件的方法。 当形成设备的选择特征时，使用复合间隔物结构来图案化和蚀刻层堆叠。 复合存储结构包括由第一隔离物材料层形成的第一间隔物和由第二隔离物材料层形成的第二和第三间隔物。 该方法适用于制造具有小于所使用的光刻工艺的最小可分辨特征尺寸的线和空间尺寸的装置。 此外，等于线和空间尺寸小于最小特征尺寸是可能的。 在一个实施例中，使用复合间隔结构形成双控制非易失性闪存存储元件阵列。 当形成衬底的活性区域时，具有叠层的叠层和隔离区之间的复合间隔结构有利于条之间的等长长度和隔离区。

    METHOD FOR FORMING SELF-ALIGNED DIELECTRIC CAP ABOVE FLOATING GATE
    60.
    发明申请
    METHOD FOR FORMING SELF-ALIGNED DIELECTRIC CAP ABOVE FLOATING GATE 有权
    在浮动门上形成自对准电介质盖的方法

    公开(公告)号：US20100081267A1

    公开(公告)日：2010-04-01

    申请号：US12242857

    申请日：2008-09-30

    申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

    发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/513 ,  H01L29/7881

    摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.

    摘要翻译： 一种用于制造非易失性存储元件的方法。 该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。 浮栅由多晶硅浮栅材料形成。 各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。 在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。 然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。 可以使用SPA（槽平面天线）氮化形成氮化物层。 可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。