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公开(公告)号：US08383479B2
公开(公告)日：2013-02-26
申请号：US12840081
申请日：2010-07-20
申请人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
发明人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
IPC分类号： H01L21/8247
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
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公开(公告)号：US08207036B2
公开(公告)日：2012-06-26
申请号：US12242857
申请日：2008-09-30
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/513 , H01L29/7881
摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.
摘要翻译： 一种用于制造非易失性存储元件的方法。 该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。 浮栅由多晶硅浮栅材料形成。 各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。 在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。 然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。 可以使用SPA（槽平面天线）氮化形成氮化物层。 可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。
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公开(公告)号：US20100081267A1
公开(公告)日：2010-04-01
申请号：US12242857
申请日：2008-09-30
IPC分类号： H01L21/3205
CPC分类号： H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/513 , H01L29/7881
摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.
摘要翻译： 一种用于制造非易失性存储元件的方法。 该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。 浮栅由多晶硅浮栅材料形成。 各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。 在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。 然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。 可以使用SPA（槽平面天线）氮化形成氮化物层。 可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。
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公开(公告)号：US20110020992A1
公开(公告)日：2011-01-27
申请号：US12840081
申请日：2010-07-20
申请人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
发明人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
IPC分类号： H01L21/336 , H01L21/76 , H01L21/3205
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
摘要翻译： 基于纳米结构的电荷存储区域包括在非易失性存储器件中，并与制造选择栅极和外围电路集成。 在存储器阵列区域和外围电路区域上的衬底上施加一个或多个纳米结构涂层。 提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。 在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层，以选择性地在衬底的有源区上形成纳米结构。 自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。
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公开(公告)号：US08105867B2
公开(公告)日：2012-01-31
申请号：US12468717
申请日：2009-05-19
申请人： George Matamis , Henry Chien , James K Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E Scheuerlein
发明人： George Matamis , Henry Chien , James K Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E Scheuerlein
IPC分类号： H01L21/00
CPC分类号： H01L21/20 , G11C13/0004 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要翻译： 公开了一种用于三维非易失性存储器的自对准制造工艺。 双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。 以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。 具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。 蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。 执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。 然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。
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公开(公告)号：US20100124813A1
公开(公告)日：2010-05-20
申请号：US12468717
申请日：2009-05-19
申请人： George Matamis , Henry Chien , James K. Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E. Scheuerlein
发明人： George Matamis , Henry Chien , James K. Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E. Scheuerlein
IPC分类号： H01L21/20 , H01L21/3205
CPC分类号： H01L21/20 , G11C13/0004 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要翻译： 公开了一种用于三维非易失性存储器的自对准制造工艺。 双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。 以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。 具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。 蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。 执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。 然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。
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公开(公告)号：US08097498B2
公开(公告)日：2012-01-17
申请号：US12693322
申请日：2010-01-25
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
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8.发明授权Lithographically space-defined charge storage regions in non-volatile memory 有权非易失性存储器中的光刻空间定义电荷存储区域公开(公告)号：US07807529B2
公开(公告)日：2010-10-05
申请号：US11960513
申请日：2007-12-19
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.
摘要翻译： 在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。 牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。 用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。 可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。 较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。 存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域 的第一电荷存储区域。
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9.发明申请Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies 有权使用蚀刻停止技术在非易失性存储器中的复合电荷存储结构形成公开(公告)号：US20100055889A1
公开(公告)日：2010-03-04
申请号：US12615154
申请日：2009-11-09
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译： 包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。 适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。 虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。 可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。 第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。 可以增加各个存储单元尺寸的一致性。
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10.发明授权Composite charge storage structure formation in non-volatile memory using etch stop technologies 有权使用蚀刻停止技术在非易失性存储器中形成复合电荷存储结构公开(公告)号：US07939407B2
公开(公告)日：2011-05-10
申请号：US12615154
申请日：2009-11-09
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译： 包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。 适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。 虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。 可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。 第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。 可以增加各个存储单元尺寸的一致性。
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