公开(公告)号：US06893930B1

公开(公告)日：2005-05-17

申请号：US10161452

申请日：2002-05-31

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/66598 ,  H01L21/26513 ,  H01L29/665 ,  H01L29/6653

Abstract: For fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on the active device area of the semiconductor substrate. Antimony (Sb) dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form at least one of drain and source extension junctions and/or drain and source contact junctions. A low temperature thermal anneal process at a temperature less than about 950° Celsius is performed for activating the antimony (Sb) dopant within the drain and source extension junctions and/or drain and source contact junctions. In one embodiment of the present invention, the drain and source contact junctions are formed and thermally annealed before the formation of the drain and source extension junctions in a disposable spacer process for further minimizing heating of the drain and source extension junctions. In another embodiment of the present invention, the drain and source extension junctions and/or the drain and source contact junctions are formed to be amorphous before the thermal anneal process. In that case, a SPE (solid phase epitaxy) activation process in performed for activating the antimony (Sb) dopant within the amorphous drain and source extension junctions and/or the amorphous drain and source contact junctions at a temperature less than about 650° Celsius.

Abstract translation: 为了在半导体衬底的有源器件区域上制造场效应晶体管，在半导体衬底的有源器件区域上形成栅极电介质和栅电极。 将锑（Sb）掺杂剂注入到半导体衬底的有源器件区域的暴露区域中，以形成漏极和源极延伸结和/或漏极和源极接触结中的至少一个。 在低于约950℃的温度下进行低温热退火工艺，以激活漏极和源极延伸结和/或漏极和源极接触接点内的锑（Sb）掺杂剂。 在本发明的一个实施例中，在一次性间隔器工艺中形成漏极和源极延伸接头之前，形成漏极和源极接触接头并进行热退火，以进一步最小化漏极和源极延伸接点的加热。 在本发明的另一实施例中，在热退火工艺之前，将漏极和源极延伸接头和/或漏极和源极接触接点形成为非晶体。 在这种情况下，在低于约650℃的温度下，在非晶漏极和源极延伸结和/或非晶漏极和源极接触点内激活用于激活锑（Sb）掺杂剂的SPE（固相外延）激活过程 。

公开(公告)号：US06872647B1

公开(公告)日：2005-03-29

申请号：US10429780

申请日：2003-05-06

Applicant: Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery

Inventor： Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery

IPC: H01L21/033 ,  H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L21/3205 ,  H01L21/20 ,  H01L21/311

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/0337 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming multiple fins in a semiconductor device includes forming a structure having an upper surface and side surfaces on the semiconductor device. The semiconductor device includes a conductive layer located below the structure. The method also includes forming spacers adjacent the structure and selectively etching the spacers and the conductive layer to form the fins. The fins may be used in a FinFET device.

Abstract translation: 在半导体器件中形成多个散热片的方法包括形成具有半导体器件上表面和侧表面的结构。 半导体器件包括位于结构下方的导电层。 该方法还包括在该结构附近形成间隔物并选择性地蚀刻间隔物和导电层以形成翅片。 翅片可用于FinFET器件。

公开(公告)号：US06855583B1

公开(公告)日：2005-02-15

申请号：US10633503

申请日：2003-08-05

Applicant: Zoran Krivokapic ,  Judy Xilin An ,  Bin Yu

Inventor： Zoran Krivokapic ,  Judy Xilin An ,  Bin Yu

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method forming a tri-gate fin field effect transistor includes forming an oxide layer over a silicon-on-insulator wafer comprising a silicon layer, and etching the silicon and oxide layers using a rectangular mask to form a mesa. The method further includes etching a portion of the mesa using a second mask to form a fin, forming a gate dielectric layer over the fin, and forming a tri-gate over the fin and the gate dielectric layer.

Abstract translation: 形成三栅极鳍场效应晶体管的方法包括在包括硅层的绝缘体上硅晶片上形成氧化物层，并且使用矩形掩模蚀刻硅和氧化物层以形成台面。 该方法还包括使用第二掩模蚀刻台面的一部分以形成翅片，在翅片上形成栅极电介质层，并在鳍状物和栅极介电层上形成三栅极。

公开(公告)号：US06812119B1

公开(公告)日：2004-11-02

申请号：US10614052

申请日：2003-07-08

Applicant: Shibly S. Ahmed ,  Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L213205

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/7842

Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

Abstract translation: 一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。 该方法还包括在每个双盖的侧面上形成间隔物，并在双重帽下面的第一半导体材料层中形成双翅片。 该方法还包括使双翅片变薄以产生窄的双翅片。

公开(公告)号：US06806147B1

公开(公告)日：2004-10-19

申请号：US10211190

申请日：2002-08-01

Applicant: Bin Yu ,  Che-Hoo Ng

Inventor： Bin Yu ,  Che-Hoo Ng

IPC: H01L21336

CPC classification number: H01L29/1079 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092

Abstract: The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then formed below the buried amorphous layer. The substrate is then subjected to a rapid thermal anneal to recrystallize the buried amorphous layer. The well structure is formed by the shallow well and the deep well. A conventional semiconductor device may then be formed above the well structure. The buried amorphous layer suppresses the channeling effect during the forming of the deep well without requiring a tilt angle.

Abstract translation: 本发明提供了用于电分离n沟道和p沟道MOSFET的改进的阱结构。 本发明首先在基底中形成浅井。 然后在浅井下面形成掩埋非晶层。 然后在埋入的非晶层下方形成深井。 然后对衬底进行快速热退火以使埋入的非晶层重结晶。 井结构由浅井和深井组成。 然后可以在阱结构之上形成常规的半导体器件。 掩埋非晶层在形成深井期间抑制沟道效应，而不需要倾斜角。

公开(公告)号：US06787406B1

公开(公告)日：2004-09-07

申请号：US10638334

申请日：2003-08-12

Applicant: Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66803 ,  Y10S438/944

Abstract: A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.

Abstract translation: 一种方法有助于掺杂包括衬底的半导体器件的散热片。 该方法包括在基板上形成翅片结构，其中每个翅片结构都包括形成在翅片上的盖。 该方法还包括执行第一倾斜角度注入工艺以用n型杂质掺杂第一个翅片，并执行第二倾斜角度注入工艺，以使p型杂质掺杂第二个翅片。

公开(公告)号：US06785240B1

公开(公告)日：2004-08-31

申请号：US09585738

申请日：2000-06-02

Applicant: Jin Cao ,  R. Drew Davis ,  Scott Alan Vander Wiel ,  Bin Yu

Inventor： Jin Cao ,  R. Drew Davis ,  Scott Alan Vander Wiel ,  Bin Yu

IPC: H04J116

CPC classification number: H04L43/067 ,  H04L41/0213 ,  H04L41/142 ,  H04L41/16 ,  H04L43/045 ,  H04L43/0888

Abstract: In many packetized communication networks, it is not feasible to obtain exact counts of traffic (OD counts) between specific origin-destination node pairs, because the link counts that are readily obtainable at router interfaces are aggregated indiscriminately over OD pairs. The best that can be done is to make a probabilistic inference concerning the OD counts from the observed link counts. Such an inference relies upon a known linear relationship between observed link counts and unknown OD counts, and a statistical model describing how the values of the OD and link counts are probabilistically distributed. Disclosed is an improved method for making such inferences. The disclosed method takes explicit account of past data when forming a current estimate of the OD counts. As a consequence, behavior that evolves in time is described with improved accuracy and smoothness.

Abstract translation: 在许多打包通信网络中，在特定的起始 - 目的地节点对之间获得精确的业务计数（OD计数）是不可行的，因为在路由器接口上容易获得的链路计数在OD对上不加区分地聚合。 可以做的最好的事情是从观察到的链接数量中对OD计数进行概率推断。 这样的推论依赖于观察到的链接计数和未知OD计数之间已知的线性关系，以及描述OD和链接计数值如何概率分布的统计模型。 公开了一种用于进行这种推断的改进方法。 当形成OD计数的当前估计时，所公开的方法明确地考虑过去数据。 因此，在时间上演变的行为以提高的准确性和平滑性来描述。

公开(公告)号：US06764908B1

公开(公告)日：2004-07-20

申请号：US10173770

申请日：2002-06-19

Applicant: Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

Inventor： Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L29/1054 ,  H01L21/823807

Abstract: A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：（a）提供包括上部，拉伸应变晶格半导体层和下部未应力半导体层的半导体衬底; 和（b）在拉伸应变晶格半导体层上或其内形成至少一个MOS晶体管，其中所述形成包括通过调整拉伸应变晶格半导体层的厚度来调节所述至少一个MOS晶体管的驱动电流的步骤。 实施例包括形成在包括与渐变组合物Si-Ge层晶格匹配的应变Si层的衬底中的CMOS器件，其中调节每个PMOS晶体管和NMOS晶体管的应变Si层的厚度以提供每个晶体管类型的最大驱动 当前。

公开(公告)号：US06762483B1

公开(公告)日：2004-07-13

申请号：US10348910

申请日：2003-01-23

Applicant: Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

Inventor： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

IPC: H01L2906

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

Abstract translation: 一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。 该方法还包括在每个双盖的侧面上形成间隔物，并在双盖下方的第一半导体材料中形成双翅片。 该方法还包括使双翅片变薄以产生窄的双翅片。

公开(公告)号：US06756643B1

公开(公告)日：2004-06-29

申请号：US10459579

申请日：2003-06-12

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L21/3212 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681

Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

Abstract translation: FinFET型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。 半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。