公开(公告)号：US06908866B2

公开(公告)日：2005-06-21

申请号：US10775515

申请日：2004-02-10

申请人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： C23C16/32 ,  C30B25/02 ,  H01L21/31 ,  H01L21/469

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些外延SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3， 生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃

公开(公告)号：US06524935B1

公开(公告)日：2003-02-25

申请号：US09675840

申请日：2000-09-29

申请人： Donald F. Canaperi ,  Jack Oon Chu ,  Christopher P. D'Emic ,  Lijuan Huang ,  John Albrecht Ott ,  Hon-Sum Philip Wong

发明人： Donald F. Canaperi ,  Jack Oon Chu ,  Christopher P. D'Emic ,  Lijuan Huang ,  John Albrecht Ott ,  Hon-Sum Philip Wong

IPC分类号： H01L2136

CPC分类号： H01L21/76254

摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) is described incorporating growing epitaxial Si1−yGey layers on a semiconductor substrate, implanting hydrogen into a selected Si1−yGey layer to form a hydrogen-rich defective layer, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and separating two substrates at the hydrogen-rich defective layer. The separated substrates may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC.

摘要翻译： 描述了在半导体衬底上生长的外延Si1-yGey层上生长在绝缘体上的弛豫SiGe（SGOI）上形成应变Si或SiGe的方法，将氢注入到选定的Si1-yGey层中以形成富氢缺陷层， 通过化学机械抛光，通过热处理将两个基板结合在一起，并在富氢缺陷层处分离两个基板。 分离的衬底可以通过CMP平滑CMP的上表面，用于外延沉积弛豫Si1-yGey，并且应变Si1-yGey取决于组成，应变Si，应变SiC，应变Ge，应变GeC和应变Si1-yGeyC。

公开(公告)号：US5780327A

公开(公告)日：1998-07-14

申请号：US840741

申请日：1997-04-16

申请人： Jack Oon Chu ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Yuan-Chen Sun ,  Yuan Taur

发明人： Jack Oon Chu ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Yuan-Chen Sun ,  Yuan Taur

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66666 ,  H01L29/7827 ,  H01L29/78612 ,  H01L29/78642

摘要： A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.

摘要翻译： 垂直双栅极场效应晶体管包括在体或SOI衬底上排列成堆叠的源极层，外延沟道层和漏极层。 栅极氧化物使用差分氧化速率在堆叠的侧面热生长以最小化输入电容问题。 栅极围绕堆叠的一端缠绕，而在第二端形成触点。 嵌入堆叠的第二端的蚀刻停止层使得能够直接与沟道层进行接触。

公开(公告)号：US07790566B2

公开(公告)日：2010-09-07

申请号：US12051366

申请日：2008-03-19

申请人： Jack Oon Chu ,  Deborah Ann Neumayer

发明人： Jack Oon Chu ,  Deborah Ann Neumayer

IPC分类号： H01L21/76

CPC分类号： C30B25/18 ,  C30B29/08 ,  Y10S438/933

摘要： A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.

摘要翻译： 公开了制备用于外延沉积的III-V族化合物半导体的表面的方法。 III-V族半导体表面在约250℃至约350℃的温度下用硼（B）处理。用于供应B用于表面处理的合适形式是乙硼烷。 B处理可以在与B处理类似的温度下进行外延生长，例如通过IV族半导体。 该方法产生高质量异质结，适用于制造各种器件结构。

公开(公告)号：US07679121B2

公开(公告)日：2010-03-16

申请号：US12114168

申请日：2008-05-02

申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

IPC分类号： H01L27/108

CPC分类号： H01L29/7781 ,  H01L29/161 ,  H01L29/165 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/7789 ,  H01L29/7828 ,  H01L29/78642 ,  H01L29/78687

摘要： A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

摘要翻译： 描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变垂直沟道的方法，其中在垂直单晶半导体结构的侧壁上结合有漏极，主体和源极区域，其中异质结 形成在晶体管的源极和主体之间，其中源极区域和沟道相对于主体区域独立地晶格应变，并且其中漏极区域包含碳掺杂区域以防止掺杂剂（硼）扩散到体内。 本发明通过异质结和晶格应变来减少来自源极区域的漏电流的问题，同时通过选择半导体材料独立地允许沟道区域中的晶格应变以增加迁移率。

公开(公告)号：US07563657B2

公开(公告)日：2009-07-21

申请号：US11971392

申请日：2008-01-09

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7842 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696

摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

摘要翻译： 公开了用于增强的FET器件的制造结构和方法，其中防止掺杂剂杂质通过栅极绝缘体扩散。 该结构包括夹在栅极绝缘体和掺杂有杂质的层之间的Si：C或SiGe：C层，以提供预选的功函数。 还进一步公开了如何以及对FET器件的进一步改进，诸如凸起源极/漏极和绝缘体上的多面绝缘体，绝缘体上的MODFET与应变的基于Si的绝缘体上的技术集成。

公开(公告)号：US20090026459A1

公开(公告)日：2009-01-29

申请号：US12163389

申请日：2008-06-27

申请人： Jack Oon Chu ,  Basanth Jaqannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jaqannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： H01L29/04

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些外延SiC和SiGeC膜原位掺杂p型或n型，并且存在低浓度的碳<1020cm-3，生长的p型或n型掺杂剂分布可以承受炉退火 到850℃的温度和快速热退火温度至1000℃

公开(公告)号：US20080248616A1

公开(公告)日：2008-10-09

申请号：US12118689

申请日：2008-05-10

申请人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

发明人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

IPC分类号： H01L21/8238 ,  H01L21/335

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7841

摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

公开(公告)号：US20080237637A1

公开(公告)日：2008-10-02

申请号：US12114168

申请日：2008-05-02

申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

IPC分类号： H01L29/165

CPC分类号： H01L29/7781 ,  H01L29/161 ,  H01L29/165 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/7789 ,  H01L29/7828 ,  H01L29/78642 ,  H01L29/78687

摘要： A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

摘要翻译： 描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变垂直沟道的方法，其中在垂直单晶半导体结构的侧壁上结合有漏极，主体和源极区域，其中异质结 形成在晶体管的源极和主体之间，其中源极区域和沟道相对于主体区域独立地晶格应变，并且其中漏极区域包含碳掺杂区域以防止掺杂剂（硼）扩散到体内。 本发明通过异质结和晶格应变来减少来自源极区域的漏电流的问题，同时通过选择半导体材料独立地允许沟道区域中的晶格应变以增加迁移率。

公开(公告)号：US07427773B2

公开(公告)日：2008-09-23

申请号：US10948421

申请日：2004-09-23

申请人： Jack Oon Chu ,  David R. DiMilia ,  Lijuan Huang

发明人： Jack Oon Chu ,  David R. DiMilia ,  Lijuan Huang

IPC分类号： H01L29/737

CPC分类号： H01L21/76256 ,  H01L21/2007

摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1−yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.

摘要翻译： 描述了在松散的SiGe绝缘体上（SGOI）上形成应变Si或SiGe的方法或Si异质结构上的SiGe的方法，该方法包括生长外延Si 1-y Ge层 半导体衬底，通过化学机械抛光的平滑表面，通过热处理将两个衬底结合在一起，并且通过使用SiGe本身作为蚀刻停止层的高选择性蚀刻将SiGe层从一个衬底转移到另一衬底。 转移的SiGe层可以通过CMP平滑其上表面，用于外延沉积弛豫的Si 1-y Ge y Si，并且应变Si 1-y