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    HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL BANDGAP ENGINEERING AND METHODS THEREOF
    3.
    发明申请
    HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL BANDGAP ENGINEERING AND METHODS THEREOF 有权
    通过二维带隙工程实现的高速横向异相MISFET及其方法

    公开(公告)号：US20100159658A1

    公开(公告)日：2010-06-24

    申请号：US12534562

    申请日：2009-08-03

    申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

    发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/802 ,  Y10S438/933

    摘要： A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

    摘要翻译： 描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变横向沟道结构的方法，其在单晶半导体衬底上结合了漏极，主体和源极区域，其中在 晶体管的源极和主体，其中源极区域和沟道独立地相对于身体区域进行晶格应变。 本发明通过异质结和晶格应变来减少来自源极区的漏电流的问题，同时通过选择半导体材料和合金组成独立地允许沟道区域中的晶格应变以增加迁移率。

    High speed GE channel heterostructures for field effect devices
    4.
    发明授权
    High speed GE channel heterostructures for field effect devices 有权
    用于场效应装置的高速GE通道异质结构

    公开(公告)号：US07608496B2

    公开(公告)日：2009-10-27

    申请号：US12209757

    申请日：2008-09-12

    申请人： Jack Oon Chu

    发明人： Jack Oon Chu

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7782 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66431

    摘要： A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.

    摘要翻译： 一种用于形成高迁移率Ge沟道场效应晶体管的方法和分层异质结构被描述为在半导体衬底上并入多个半导体层，以及具有较高势垒或更深限制量子阱的压缩应变外延Ge层的沟道结构， 对互补的MODFET和MOSFET具有极高的空穴迁移率。 本发明克服了由于仅具有单个压缩应变SiGe沟道层的p沟道器件的合金散射引起的有限空穴迁移率的问题。 本发明还提供了在深亚微米级的最先进的Si pMOSFETs的迁移率和跨导性方面的改进，以及从室温（425K）到低温低温（0.4K）的宽温度操作方案，其中在低温 甚至可以实现高设备性能。

    HIGH SPEED GE CHANNEL HETEROSTRUCTURES FOR FIELD EFFECT DEVICES
    6.
    发明申请
    HIGH SPEED GE CHANNEL HETEROSTRUCTURES FOR FIELD EFFECT DEVICES 有权
    用于场效应器件的高速GE通道异构体

    公开(公告)号：US20090081839A1

    公开(公告)日：2009-03-26

    申请号：US12209757

    申请日：2008-09-12

    申请人： Jack Oon Chu

    发明人： Jack Oon Chu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7782 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66431

    摘要： A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.

    摘要翻译： 一种用于形成高迁移率Ge沟道场效应晶体管的方法和分层异质结构被描述为在半导体衬底上并入多个半导体层，以及具有较高势垒或更深限制量子阱的压缩应变外延Ge层的沟道结构， 对互补的MODFET和MOSFET具有极高的空穴迁移率。 本发明克服了由于仅具有单个压缩应变SiGe沟道层的p沟道器件的合金散射引起的有限空穴迁移率的问题。 本发明进一步提供了在深亚微米级的最先进的Si pMOSFETs的迁移率和跨导性方面的改进，以及从室温（425K）到低温低温（0.4K）的宽温度操作方案，其中在低温下 甚至可以实现高设备性能。

    Method for metal gated ultra short MOSFET devices
    7.
    发明授权
    Method for metal gated ultra short MOSFET devices 失效
    金属门极超短MOSFET器件的方法

    公开(公告)号：US07494861B2

    公开(公告)日：2009-02-24

    申请号：US12013704

    申请日：2008-01-14

    申请人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

    发明人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7838 ,  H01L21/28017 ,  H01L29/105

    摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

    摘要翻译： 适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。 体层掺杂了与地平面相反的杂质。 栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。 栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。 在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

    Transferable device-containing layer for silicon-on-insulator applications
    9.
    发明授权
    Transferable device-containing layer for silicon-on-insulator applications 有权

    公开(公告)号：US06774010B2

    公开(公告)日：2004-08-10

    申请号：US09769170

    申请日：2001-01-25

    申请人： Jack Oon Chu ,  Alfred Grill ,  Dean A. Herman, Jr. ,  Katherine L. Saenger

    发明人： Jack Oon Chu ,  Alfred Grill ,  Dean A. Herman, Jr. ,  Katherine L. Saenger

    IPC分类号： H01L2972

    CPC分类号： H01L27/1203 ,  H01L21/76259

    摘要： A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a “transferable” device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer. The at least partially crystalline porous layer may incorporate at least one porous silicon germanium alloy layer alone or in combination with at least one porous Si layer. Also described is an integrated circuit comprising the transfered device layer described above.