公开(公告)号：US20090026459A1

公开(公告)日：2009-01-29

申请号：US12163389

申请日：2008-06-27

申请人： Jack Oon Chu ,  Basanth Jaqannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jaqannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： H01L29/04

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些外延SiC和SiGeC膜原位掺杂p型或n型，并且存在低浓度的碳<1020cm-3，生长的p型或n型掺杂剂分布可以承受炉退火 到850℃的温度和快速热退火温度至1000℃

公开(公告)号：US06908866B2

公开(公告)日：2005-06-21

申请号：US10775515

申请日：2004-02-10

申请人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： C23C16/32 ,  C30B25/02 ,  H01L21/31 ,  H01L21/469

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些外延SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3， 生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃

公开(公告)号：US07183576B2

公开(公告)日：2007-02-27

申请号：US10775514

申请日：2004-02-10

申请人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： H01L29/16 ,  H01L29/737

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些成膜SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3， 生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃

公开(公告)号：US06750119B2

公开(公告)日：2004-06-15

申请号：US09838892

申请日：2001-04-20

申请人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： H01L2120

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

公开(公告)号：US06475072B1

公开(公告)日：2002-11-05

申请号：US09675841

申请日：2000-09-29

申请人： Donald F. Canaperi ,  Jack Oon Chu ,  Guy M. Cohen ,  Lijuan Huang ,  John Albrecht Ott ,  Michael F. Lofaro

发明人： Donald F. Canaperi ,  Jack Oon Chu ,  Guy M. Cohen ,  Lijuan Huang ,  John Albrecht Ott ,  Michael F. Lofaro

IPC分类号： B24B100

CPC分类号： H01L21/02074 ,  B24B37/345 ,  B24B49/006 ,  H01L21/02052 ,  H01L21/02065 ,  H01L21/31053 ,  H01L21/76251

摘要： A method and apparatus is described incorporating a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool. The CMP is performed with a down force of 1 psi, a backside air pressure of 0.5 psi, a platen speed of 50 rpm, a crarrier speed of 30 rpm and a slurry flow rate of 140 milliliters per minute.

摘要翻译： 描述了结合半导体衬底，CMP工具，刷子清洁工具和化学晶片清洁工具的方法和装置。 CMP的下压力为1psi，背面空气压力为0.5psi，压板速度为50rpm，碎屑速度为30rpm，淤浆流速为140毫升/分钟。

公开(公告)号：US06251751B1

公开(公告)日：2001-06-26

申请号：US09290778

申请日：1999-04-13

申请人： Jack Oon Chu ,  Khalid Ezzeldin Ismail ,  Kim Yang Lee ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Khalid Ezzeldin Ismail ,  Kim Yang Lee ,  John Albrecht Ott

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76281

摘要： A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

摘要翻译： 一种用于在单晶半导体层下面形成掩埋氧化物区域的方法，其包括形成具有不同氧化速率的外延层的步骤，下层具有较快的氧化速率和通过掩模中的开口氧化该层。 可以形成多个氧化物隔离FET。 通过选择性地氧化半导体层，本发明减少了源极/漏极寄生电容和短沟道效应的问题，同时隔离FET并消除FET的浮体效应。

公开(公告)号：US06524935B1

公开(公告)日：2003-02-25

申请号：US09675840

申请日：2000-09-29

申请人： Donald F. Canaperi ,  Jack Oon Chu ,  Christopher P. D'Emic ,  Lijuan Huang ,  John Albrecht Ott ,  Hon-Sum Philip Wong

发明人： Donald F. Canaperi ,  Jack Oon Chu ,  Christopher P. D'Emic ,  Lijuan Huang ,  John Albrecht Ott ,  Hon-Sum Philip Wong

IPC分类号： H01L2136

CPC分类号： H01L21/76254

摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) is described incorporating growing epitaxial Si1−yGey layers on a semiconductor substrate, implanting hydrogen into a selected Si1−yGey layer to form a hydrogen-rich defective layer, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and separating two substrates at the hydrogen-rich defective layer. The separated substrates may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC.

摘要翻译： 描述了在半导体衬底上生长的外延Si1-yGey层上生长在绝缘体上的弛豫SiGe（SGOI）上形成应变Si或SiGe的方法，将氢注入到选定的Si1-yGey层中以形成富氢缺陷层， 通过化学机械抛光，通过热处理将两个基板结合在一起，并在富氢缺陷层处分离两个基板。 分离的衬底可以通过CMP平滑CMP的上表面，用于外延沉积弛豫Si1-yGey，并且应变Si1-yGey取决于组成，应变Si，应变SiC，应变Ge，应变GeC和应变Si1-yGeyC。

公开(公告)号：US5963817A

公开(公告)日：1999-10-05

申请号：US951827

申请日：1997-10-16

申请人： Jack Oon Chu ,  Khalid Ezzeldin Ismail ,  Kim Yang Lee ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Khalid Ezzeldin Ismail ,  Kim Yang Lee ,  John Albrecht Ott

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/108 ,  H01L21/76

CPC分类号： H01L21/76264 ,  H01L21/76281

摘要： A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

摘要翻译： 一种用于在单晶半导体层下面形成掩埋氧化物区域的方法，其包括形成具有不同氧化速率的外延层的步骤，下层具有较快的氧化速率和通过掩模中的开口氧化该层。 可以形成多个氧化物隔离FET。 通过选择性地氧化半导体层，本发明减少了源极/漏极寄生电容和短沟道效应的问题，同时隔离FET并消除FET的浮体效应。

公开(公告)号：US06805962B2

公开(公告)日：2004-10-19

申请号：US10055138

申请日：2002-01-23

申请人： Stephen W. Bedell ,  Jack O. Chu ,  Keith E. Fogel ,  Steven J. Koester ,  Devendra K. Sadana ,  John Albrecht Ott

发明人： Stephen W. Bedell ,  Jack O. Chu ,  Keith E. Fogel ,  Steven J. Koester ,  Devendra K. Sadana ,  John Albrecht Ott

IPC分类号： B32B900

CPC分类号： H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/2251 ,  H01L21/324 ,  H01L27/1203 ,  H01L29/66916 ,  Y10S438/938 ,  Y10T428/12674 ,  Y10T428/265 ,  Y10T428/31848

摘要： A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to the diffusion of Ge. Optionally forming a Si cap layer over the SiGe or pure Ge layer, and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughout the first single crystal Si layer, the optional Si cap and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate materials are also disclosed herein.

摘要翻译： 提供一种形成薄的，高质量的松散的绝缘体上硅衬底材料的方法，其首先包括在第一单晶Si层的表面上形成SiGe或纯Ge层，该第一单晶Si层存在于阻挡层上 对Ge的扩散。 可选择地在SiGe或纯Ge层上形成Si覆盖层，然后在允许Ge遍及第一单晶Si层的相互扩散的温度下加热各层，任选的Si盖和SiGe或纯Ge层，从而形成 基本上松弛的单晶SiGe层在阻挡层顶上。 附加的SiGe再生长和/或应变外延层的形成可以遵循上述步骤。 绝缘体上硅衬底材料以及至少包括绝缘体上硅衬底材料的结构也在本文中公开。

公开(公告)号：US07550369B2

公开(公告)日：2009-06-23

申请号：US11873928

申请日：2007-10-17

申请人： Joel Pereira de Souza ,  Keith Edward Fogel ,  John Albrecht Ott ,  Devendra Kumar Sadana ,  Katherine Lynn Saenger

发明人： Joel Pereira de Souza ,  Keith Edward Fogel ,  John Albrecht Ott ,  Devendra Kumar Sadana ,  Katherine Lynn Saenger

IPC分类号： H01L21/20

CPC分类号： H01L21/26506 ,  H01L21/2022

摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.

摘要翻译： 本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向 具有不同的方向。 更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶 非晶层的原始方向。 本发明方法的关键部件是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以消除在初始再结晶退火之后残留的缺陷。 本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。