公开(公告)号：US10236367B2

公开(公告)日：2019-03-19

申请号：US15642732

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Shiv Kumar Mishra

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266

Abstract: A device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction. The second well includes a silicon alloy portion displaced from the PN junction. A collector region contacts one of the first or second wells and has a dopant concentration higher than its contacted well. An emitter region contacts the other of the first or second wells and is doped with dopants of the first or second conductivity type different than the first or second well contacted by the emitter region. A base region contacts the other of the first or second well and has a dopant concentration higher than the first or second well contacted by the base region.

公开(公告)号：US20190013402A1

公开(公告)日：2019-01-10

申请号：US15642675

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Shiv Kumar Mishra

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction between the first and second wells. The second well includes a silicon alloy portion displaced from the PN junction. A source region is positioned in one of the first well or the second well. A drain region is positioned in the other of the first well or the second well. A gate structure is positioned above the substrate laterally positioned between the source region and the drain region.

公开(公告)号：US09966459B2

公开(公告)日：2018-05-08

申请号：US14476976

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Biswanath Senapati ,  Jagar Singh

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L27/06 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L29/417 ,  H01L29/423 ,  H01L27/02

CPC classification number: H01L29/735 ,  G01R31/2621 ,  G01R31/2884 ,  H01L22/34 ,  H01L27/0259 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/42304

Abstract: A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.

公开(公告)号：US09905668B2

公开(公告)日：2018-02-27

申请号：US15057791

申请日：2016-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/45 ,  H01L29/40 ,  H01L29/735 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/66325 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7393

Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.

公开(公告)号：US20180006019A1

公开(公告)日：2018-01-04

申请号：US15686523

申请日：2017-08-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kasun Anupama Punchihewa ,  Jagar Singh

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/265 ,  H01L27/08 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/26513 ,  H01L21/823431 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66136 ,  H01L29/861

Abstract: A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of the plurality of fins and in a second surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins. The doped region includes a first dopant having a first conductivity type and is contiguous between the adjacent fins. A cathode region is defined by an inner portion of each of the plurality of fins positioned below and contacting the first surface portion and a third portion of the semiconductor substrate positioned below and contacting the second surface portion. The cathode region is contiguous and the dopants in the cathode region and anode region have opposite conductivity types. A junction is defined between the anode region and the cathode region. A first contact interfaces with the anode region.

公开(公告)号：US09773781B1

公开(公告)日：2017-09-26

申请号：US15342498

申请日：2016-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jagar Singh ,  Jerome Ciavatti

IPC: H01L29/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A first capacitor plate is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. An insulator layer and a second capacitor plate are disposed on the first capacitor plate forming a MIM capacitor. A pair of capacitor plate contacts are electrically connected to the first capacitor plate and the second capacitor plate.

公开(公告)号：US20160190229A1

公开(公告)日：2016-06-30

申请号：US14584068

申请日：2014-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L21/823431 ,  H01L27/0629 ,  H01L27/0738 ,  H01L27/0802 ,  H01L27/101 ,  H01L29/7831 ,  H01L29/785

Abstract: A resistor device includes a resistor body disposed in a substrate and doped with a first type of dopant, an insulating layer disposed above the resistor body, and at least one gate structure disposed above the insulating layer and above the resistor body. A method includes applying a bias voltage to at least a first gate structure disposed above an insulating layer disposed above a resistor body disposed in a substrate and doped with a first type of dopant to affect a resistance of the resistor body.

Abstract translation: 电阻器装置包括设置在衬底中并掺杂有第一类型掺杂剂的电阻体，设置在电阻体上方的绝缘层，以及设置在绝缘层上方和电阻体上方的至少一个栅极结构。 一种方法包括将偏置电压施加到至少第一栅极结构，该至少第一栅极结构设置在设置在衬底上的电阻体上方的绝缘层上方并掺杂有第一类型掺杂剂以影响电阻体的电阻。

公开(公告)号：US20160190120A1

公开(公告)日：2016-06-30

申请号：US14583943

申请日：2014-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/66795

Abstract: A resistor device includes a resistor body doped with a first type of dopant, an insulating layer disposed above the resistor body, and at least one gate structure disposed above the insulating layer and above the resistor body. A method includes applying a bias voltage to at least a first gate structure disposed above an insulating layer disposed above a resistor body doped with a first type of dopant to affect a resistance of the resistor body.

Abstract translation: 电阻器件包括掺杂有第一类型掺杂剂的电阻体，设置在电阻体上方的绝缘层，以及设置在绝缘层之上和电阻体上方的至少一个栅极结构。 一种方法包括：将至少第一栅极结构施加偏压，所述至少第一栅极结构设置在设置在掺杂有第一类型掺杂剂的电阻体上方的绝缘层上方，以影响电阻体的电阻。

公开(公告)号：US09312371B2

公开(公告)日：2016-04-12

申请号：US14339505

申请日：2014-07-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/735 ,  H01L29/739 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/66325 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7393

Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.

Abstract translation: 本文提供了一种包括双极结型晶体管及其制造方法的结构。 双极结型晶体管包括：包括具有第一导电类型的衬底区域的衬底; 在所述衬底区域的第一部分上方的发射极区域，所述发射极区域具有第二导电类型; 位于所述衬底区域的第二部分上方的集电极区域，所述集电极区域具有所述第二导电类型; 以及设置在所述衬底区域的一部分上的基底区域叠层结构。 基极区叠层结构将发射极区域与集电极区分开，并且在衬底区域内的衬底区域的第一部分和第二部分之间对准至双极结晶体管的基极区域。

公开(公告)号：US09263385B1

公开(公告)日：2016-02-16

申请号：US14589011

申请日：2015-01-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Anurag Mittal

IPC: H01L23/525 ,  H01L23/538 ,  H01L21/62 ,  H01L21/71 ,  H01L27/24 ,  H01L21/768 ,  H01L29/417 ,  H01L29/45 ,  H01L29/8605 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L21/823431 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor fuses with epitaxial fuse link regions and fabrication methods thereof are presented. The methods include: fabricating a semiconductor fuse including an anode region and a cathode region electrically linked by a fuse link region, and the fabricating including: forming, epitaxially, the fuse link region between the anode region and the cathode region, wherein the fuse link region facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region thereof. The semiconductor fuses include: an anode region and a cathode region electrically linked by a fuse link region, wherein the fuse link region includes an epitaxial structure and facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region, wherein the epitaxial structure is in at least partial crystallographic alignment with the anode region and the cathode region of the semiconductor fuse.

Abstract translation: 提出了具有外延熔丝链接区域的半导体熔丝及其制造方法。 所述方法包括：制造包括通过熔丝链区域电连接的阳极区域和阴极区域的半导体熔丝，所述制造方法包括：外延地形成阳极区域和阴极区域之间的熔断体区域，其中熔丝连接 区域有助于半导体熔丝开路，以在阳极区域和阴极区域之间施加编程电流。 半导体熔丝包括：通过熔丝链区域电连接的阳极区域和阴极区域，其中熔丝链路区域包括外延结构，并且有助于半导体熔丝开路以在阳极区域和阴极区域之间施加编程电流， 其中所述外延结构与半导体保险丝的阳极区域和阴极区域至少部分晶体取向。