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    FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED METAL PLUGS AND METHODS
    51.
    发明申请
    FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED METAL PLUGS AND METHODS 审中-公开

    公开(公告)号：US20200035555A1

    公开(公告)日：2020-01-30

    申请号：US16047037

    申请日：2018-07-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

    IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45

    Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.

    Method for forming replacement air gap
    53.
    发明授权
    Method for forming replacement air gap 有权

    公开(公告)号：US10535771B1

    公开(公告)日：2020-01-14

    申请号：US16016828

    申请日：2018-06-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

    IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02

    Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

    Using source/drain contact cap during gate cut
    54.
    发明授权
    Using source/drain contact cap during gate cut 有权

    公开(公告)号：US10522538B1

    公开(公告)日：2019-12-31

    申请号：US16032108

    申请日：2018-07-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

    IPC: H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

    Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

    Performing concurrent diffusion break, gate and source/drain contact cut etch processes
    55.
    发明授权
    Performing concurrent diffusion break, gate and source/drain contact cut etch processes 有权

    公开(公告)号：US10522410B2

    公开(公告)日：2019-12-31

    申请号：US15958593

    申请日：2018-04-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Haiting Wang ,  Hong Yu

    IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088

    Abstract: A device is formed including fins formed above a substrate, an isolation structure between the fins, a plurality of structures defining gate cavities, and a first dielectric material positioned between the structures. A patterning layer above the first dielectric material and in the gate cavities has a first opening positioned above a first gate cavity exposing a portion of the isolation structure and defining a first recess, a second opening above a second gate cavity exposing a first portion of the fins, and a third opening above a first portion of a source/drain region in the fins to expose the first dielectric material. Using the patterning layer, a second recess is formed in the substrate and a third recess is defined in the first dielectric material. A second dielectric material is formed in the recesses to define a gate cut structure, a diffusion break structure, and a contact cut structure.

    METHOD FOR FORMING REPLACEMENT AIR GAP
    56.
    发明申请
    METHOD FOR FORMING REPLACEMENT AIR GAP 审中-公开

    公开(公告)号：US20190393335A1

    公开(公告)日：2019-12-26

    申请号：US16016828

    申请日：2018-06-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

    Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

    Gate cut integration and related device
    60.
    发明授权
    Gate cut integration and related device 有权

    公开(公告)号：US10056469B1

    公开(公告)日：2018-08-21

    申请号：US15430647

    申请日：2017-02-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui-feng Li ,  Laertis Economikos

    IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/02

    Abstract: A method for forming gate cuts during RMG processing and the resulting device are provided. Embodiments include forming Si fins over a substrate; forming a STI layer over the substrate and recessed, exposing upper portions of the Si fins; forming polysilicon dummy gate electrodes perpendicular to the Si fins, separated by STI regions, on the upper portions of the Si fins and on the STI layer between the Si fins; forming a hardmask over the polysilicon dummy gate electrodes; etching through the hardmask and polysilicon dummy gate electrodes forming cavities between some of the Si fins; oxidizing polysilicon exposed on sides of the cavities and any residual polysilicon remaining at a bottom of one or more of the cavities; filling the cavities with SiN; removing the polysilicon dummy gate electrodes; and forming RMGs.

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